OBJECTIVE

IMPLEMENTATION FOR ERROR-TOLERANT

APPLICATIONS

 To Reduce the Power consumption

 To Reduce the delay
 To increase the Speed of the operation

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 ABSTRACT
 Multiplication is a key fundamental function for many error- tolerant
application.
 Implementing multiplier to reduce critical path delay with low power
dissipation & delay.
 To develop a MAC architecture and FIR filter.

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LITERATURE SURVEY
S.N Title of the Author Name Methodolog
Advantage Disadvantage
O paper (Year) y
1 A Low- power, C. Liu, J. Han, and Accuracy Delay is Power
High performance F. Lombardi controllable very much dissipation is
approximate (2014). multiplier reduced. increased.
multiplier with
configurable
partial error
recovery.
2 Design and A. Momeni, Delay is It can be used
analysis of J. Han, 4-2 reduced. for reduction of
approximate P. Montuschi and Compressor four
compressors for F. Lombardi approximate
multiplication. (2015). multiplier.

3 Approximate J. Han, and Image Area is Low accuracy.

compressors for F. Lombardi. sharpening reduced.
Error-Resilient (2015). algorithm
multiplier design.
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LITERATURE SURVEY
S.N Title of the Author Name Disadvantag
Methodology Advantage
O paper (Year) e
4. Analysis of K. C. Bickerstaff Wallace tree Suitable for Glitching
column E. E. Swortzlander multiplier pipeline occurs
compression M. J. Schulte. imlementati
multiplier. ons

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 EXISTING METHODOLOGY
 A CMA is proposed to control the accuracy flexibly and dynamically.

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 WALLACE MULTIPLIER

 A Wallace tree is an efficient hardware implementation of a

digital circuit that multiplies two integers.
The Wallace tree has three steps:
 Multiply each bit of one of the arguments, by each bit of the
other, yielding results.
 Reduce the number of partial products to two by layers of full
and half adders.
 Group the wires in two numbers, and add them with a
conventional adder.

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Accurate Half Adder And Incomplete Adder Cell

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Accurate Half Adder

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Incomplete Adder cell

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 Incomplete Adder Cell with 8-bit inputs

• Two 8-bit inputs:

• A={a7,a6,a5,a4,a3,a2,a1,a0} B={b7,b6,b5,b4,b3,b2,b1,b0}

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Incomplete Adder cells with 8 input

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Tree compressor with 8 inputs

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Tree Compressor with 8 input

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Carry maskable half adder

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Carry maskable full adder

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WALLACE TREE FORMATION

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PROPOSED METHODOLOGY
DADDA MULTIPLIER
n-bit Multiplier n-bit Multiplicand

Formation of partial products

using AND logic gates

Reducing the ‘n’ of partial

products to a Two-row partial
products by compressing the
column’s with adder’s

Merging two-rowed partial

products with carry skip adder

2-n bit results

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 DADDA MULTIPLIER

The Dadda multiplier is a hardware multiplier design . It is similar to

the Wallace multiplier, but it is slightly faster and requires fewer gates.
The Dadda multiplier has three stage:
Multiply each bit of w1,by each bit of w2 yielding l1.l2 results, grouped
by weight in columns.
Reduce the number of partial products by stages of full and half
adders until we are left with at most two bits of each weight.
Add the final result with a conventional adder.

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 CARRY-SKIP ADDER

A Carry skip adder is an adder implementation

that improves on the delay of the ripple –carry
adder with little effort compared to the other
adders . that improvement on the worst case
delay is achieved by using several carry-skip
adder to form a block carry-skip adder.

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CARRY-SKIP ADDER BLOCK
DIAGRAM

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REFERENCES
• Katsuhiko Wakasugi, ”A-Low power High speed Accuracy-Controllable
Multiplier Design”,IEEE Transaction on VLSI Design and Education
Center(vDEC) @2018IEEE.
• C. Liu, J. Han, and F. Lombardi, “A Low-Power, High-Performance
approximate multiplier with configurable partial error recovery,” Design,
Automation & Test in Europe Conference & Exhibition (DATE), Mar.
2014.
• A. Momeni, J. Han, P. Montuschi, and F. Lombardi, “Design and analysis
of approximate compressors for multiplication,” IEEE Transactions on
Computers, vol. 64, no. 4, pp. 984-994, Apr. 2015.
• K. C. Bickerstaff, E. E. Swartzlander, and M. J. Schulte, “Analysis of
column compression multipliers,” 15th IEEE Symposium on Computer
Arithmetic, pp. 33-39, Jun. 2010.

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THANK YOU

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