Chapter 7

Flip-Flops, Registers, Counters, and A Simple Processor

 Chapter Objectives
• In this chapter you will learn about:
• Logic circuits that can store information
• Flip-flops, which store a single bit
• Registers, which store multiple bits
• Shift registers, which shift the contents of the register
• Counters of various types
LATCH
Introduction
• In previous chapters we considered combinatorial circuits where the
value of each output depends solely on the values of signal applied to
the inputs.
Combinatorial Circuit Example
Introduction
• There exists another class of logic circuits in which the value of the
outputs depend not only on the input, but also on the past behavior
of the circuit.
• This circuits include storage elements ( the contents of this storage
element are said to represent the state of the circuit)
Introduction…
• When the circuit’s input change values, the new input values either
leave the circuit in the same state or cause it to change into a new
state.
• Overtime the circuit changes through a sequence of states as a result
of changes in the inputs (This is called sequential circuits).
Source : https://www.youtube.com/watch?v=EGnXSzPV_M8
Source : https://www.electronicproducts.com/uploadedImages/Education/Design/fajb_laser_tripwire_01_jun2016.jpg
Control of an Alarm System
Control of an Alarm System
A simple memory element

Made by two inverter

Yet its not useful because it lacks some practical
means for changing it’s state…
BASIC LATCH
LATCH
• The basic element for storing information
• One latch can store 1 bit of information
The same circuit with different
arrangement
Timing diagram for the basic latch with NOR gates
GATED SR LATCH
Introduction
• It will be better if we can control the input of Basic Latch or SR Latch,
either by enabling or disabling the input for any given time.
GATED SR LATCH
GATED SR LATCH
GATED SR LATCH WITH NAND
GATES
GATED D LATCH
Introduction
• Compared to Gated SR Latch, Gated D Latch won’t have an oscillatory
output.
• Gated D Latch function as an input storage when Clk is enabled (we
can think of the sum in half-adder that will be used in subsequent
calculation).
Gated D Latch
Gated D Latch
Effects of Propagation Delay
• In the previous discussion we ignored the effects of propagation
delays.
• In practical circuits it is essential to take these delays into account.
Effects of Propagation Delay…

Ideal Timing Diagram, no propagation delay.

Effects of Propagation Delay…
• At the time clock goes from 1 to 0, the circuit will still function
properly if the signal D remain stable during the transition.
• An unpredictable result may occur if the D signal also changes at the
time where Clk changes from 1 to 0.
• Therefore, the designer of a logic circuit that generates the D signal
must ensure that this signal is stable when the critical change in the
cock signal takes place.
Effects of Propagation Delay…
• The minimum time that the D signal must be stable prior to the
negative edge of the Clk signal is called the setup time, of the latch
• The minimum time that the D signal must remain stable after the
negative edge of the Clk signall is called the hold time, of the latch
Effects of Propagation Delay…

Setup and hold time

Effects of Propagation Delay…
• The values of and depend on the technology used.
• Manufacturers of integrated circuit chips provide this information on
the data sheets that describe their chips.
• Typical values for a modern CMOS technology may be and