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VLSI DESIGN USING


VHDL
Presented by-
ABHINAV SHUKLA
Electronics and communication engineering
Presentation Outline

 Introduction of VLSI
 What is VHDL
 Why VHDL
 VHDL within VLSI design Cycle
 Combinational & sequential circuits
 Design Hierarchy and syntax
 About Xilinx ISE
 Examples
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What is VLSI..?

VLSI is the technology of making integrated circuits (ICs) by


fabricating a large number of transistors on a single chip. Well, we
may think that how many transistors can be fabricated on a modern
IC (say on an intel corei3 microprocessor)? More than 1 billion
transistors. And, to our surprise, that many transistors are
fabricated on a few hundred (~ 100 - ~ 300) mm square area.

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What is VHDL?

 VHDL is VHSIC (Very High Speed Integrated Circuits)


Hardware Description Language
 VHDL is designed to describe the behavior of the digital
systems
 It is a design entry language
 VHDL is concurrent
 Using VHDL test benches, we can verify our design
 VHDL integrates nicely with low level design tools

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Why VHDL?

 It is IEEE standard (1076 and 1164)


 VHDL now includes VITAL (IEEE 1076.4), using which the timing information
can be implemented to a simulation model.
 VHDL has hierarchical design units
 Learning VHDL is easy.
 VHDL and Verilog are identical in functionality
 VHDL provides a wide set of different operators:
Assignment operators
Logical operators
Arithmetical operators
Relational operators
Shift operators
Concatenation operators

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VHDL Within VLSI Design
Cycle

 VLSI design starts with capturing an idea on the back of an


envelope
 From the specifications, one needs to construct a behavioral
description of the circuit
 When one describes how information flows between registers
in a design, it is called RTL (register transfer level)

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Continued….
 A structure level description defines the circuit in terms of a
collection of components
 VHDL supports behavioral, RTL and structural descriptions,
thus supporting various levels of abstraction
 Most VHDL users prefer RTL descriptions and use VHDL as
input to the synthesis process
 Synthesis tools then optimize and compile the design as per
specified constraints and map to target devices as per libraries.
 Gate level simulation is conducted to verify the design; using
the same test vectors that were generated for RTL simulation
 Finally the place and route tools are used for layout generation
and timing closure

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Combinational Logic
 Several combinational logic units are available in VHDL for
use in the designs
 A pure combinational logic circuit’s output depends on its
present input only
 A combinational circuit cannot store or buffer any values for
subsequent clock cycles. Everything must be accomplished
within the same clock cycle.
 Examples :- Multiplexer, De multiplexer, Adder etc.

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Sequential Logic
 Several sequential logic units are available in VHDL for use in
the design.
 Sequential circuits use current input variables and previous
input variables by storing the information and putting back into
the circuit on the next clock (activation) cycle.
 Examples :- Flip flops, Latch, Counter etc.

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Design Hierarchy

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VHDL Syntax

 You may use UPPERCASE for reserved words in VHDL and


lowercase words for your chosen names but it is not necessary.
 The basic building blocks of VHDL design are ENTITY
declaration and ARCHITECTURE body.
 The VHDL file name must be the same as the ENTITY name
 ENTITY declaration treats the design as a black box. It just
names the inputs and outputs as ports.
 It does not specify how the circuit works.
 The last entry in the port declaration is not followed by a
semicolon.
 Each signal has a signal mode (IN, OUT or BUFFER) and a
signal type (BIT, BIT_VECTOR, STD_LOGIC,
STD_LOGIC_VECTOR)

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Continued…

 The functional relation between the input and output


signals is described by the architecture body
 Only one architecture body should be bound to an
entity, although many architecture bodies can be
defined
 Architecture body can be written in many different
ways.

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Standard Libraries
 Include library ieee before entity declaration.
 ieee.std_logic_1164 defines a standard for designers to use in describing
interconnection data types used in VHDL modeling.
 ieee.std_logic_arith provides a set of arithmetic, conversion, comparison
functions for signed, unsigned, std_ulogic, std_logic, std_logic_vector.
 ieee.std_logic_unsigned provides a set of unsigned arithmetic, conversion, and
comparison functions for std_logic_vector.
Xilinx ISE Software

 Xilinx ISE (Integrated Synthesis Environment) is a


software tool produced by Xilinx for synthesis and
analysis of HDL designs, enabling the developer
to synthesize ("compile") their designs, perform timing
analysis, examine RTL diagrams, simulate a design's
reaction to different stimuli, and configure the target
device with the programmer.

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Example:- VHDL code for
Half adder(Combinational Circuit)

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VHDL Code

library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity half_adder is
 Port ( a : in STD_LOGIC; b : in STD_LOGIC;
 sum : out STD_LOGIC; carry : out STD_LOGIC);
 end half_adder;
 architecture Behavioral of half_adder is begin
 sum <= a xor b; carry <= a and b;
 end Behavioral;

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RTL & simulation Design

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Example:-VHDL code for D
Flip-Flop(sequential circuit)

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RTL and Simulation Design

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