Thermal Via Placement in 3D ICs

Brent Goplen, Sachin Sapatnekar

Department of Electrical and Computer Engineering
University of Minnesota

1
 Overview
 Introduction
 Simplified Example
 Formulation
 Results
 Conclusions

2
 3D IC Using Wafer Bonding
Detailed view Generalized view

Layer 5

Layer 4
SOI wafers with bulk
substrate removed
Inter-layer
bonds Layer 3

1m
Layer 2
Bulk wafer
Metal level
of wafer 1 Layer 1 10m

Bulk Substrate 500m

Device
Adapted from
level 1
[Das et al., ISVLSI, 2003] 3
Improvements and Obstacles of 3D ICs
Benefits 1400
3D Global Net Distributions
 Reduced wirelength 1200
4 Strata

Net Density (#/mm)

1000 2 Strata
 Lower power per transistor 800
1 Stratum

Decreased delay
600


400

 Higher packing densities 200

 Smaller chip areas

0 5 10 15 20 25 30 35

Length (mm)

[Joyner, Zarkesh-Ha and Meindl, ASIC/SOC ’01]

Obstacles
 Processing technology
 Thermal issues
 Higher power densities
 Increased thickness
 Insulating materials
 3D design tools
from Intel 4
Methods of Mitigating Thermal Problems

 Rearrange heat sources  Minimize power usage

 Manually fix hot spots  Low-power design
 Thermal placement  Minimize wirelength

 Improved heat sinking  Improved thermal conduits

 Improved packaging  Internal heat sinking
 More efficient heat removal  Thermal via placement

5
 Thermal Via Regions

Thermal Via

Substrate

 Thermal vias
 Electrically isolated vias
 Used for heat conduction
 Thermal via regions
 Only region where thermal vias are allowed
 Predictable obstacle for routing
 Variable density of thermal vias
6
Thermal Vias in 3D ICs

Thermal Via Region

Row Region
Inter-Row Region

Inter-layer elements
Layer elements
Standard cells (heat sources)
Bulk substrate elements

7
 Benefits and Challenges
 Benefits
 Reduced temperatures
 Uses existing via fabrication
 Benefits 3D ICs more
 Challenges
 Creates obstacles to routing
 Where to put them?
 CAD tools needed

8
 Overview
 Introduction
 Simplified Example
 Formulation
 Results
 Conclusions

9
Simplified Example
Thermal Via Regions

{
Heat Sources
(standard cells)

Layers and inter-layers

Bulk Substrate

10
Simplified Example

11
 Simplified Example
1 10oC/W 2 10oC/W 3

10oC/W 10oC/W 10oC/W

4 10oC/W 5 10oC/W 6

10W
10oC/W 10oC/W 10oC/W

7 10oC/W 8 10oC/W
9

10oC/W 10oC/W 10oC/W

10

12
 Simplified Example
65oC 10oC/W 70oC 10oC/W 65oC

10oC/W 10oC/W 10oC/W

59oC 10oC/W 81oC 10oC/W 59oC

10W
10oC/W 10oC/W 10oC/W

32oC 10oC/W 36oC 10oC/W 32oC

10oC/W 10oC/W 10oC/W

0oC

13
 Simplified Example
65oC 70oC 65oC

10oC/W 6oC 6oC 10oC/W High Temps

59oC 81oC 59oC

10W
10oC/W 27oC 27oC 10oC/W High temp drop

32oC 36oC 32oC

0oC

14
 Simplified Example
60 65oC 67 70oC 60 65oC

1 1
10oC/W 10oC/W
60
59oC 81oC 59oC 60

32oC 36oC 32oC

0oC

15
 Simplified Example
44 65oC 51 70oC 44 65oC

Use thermal gradient

not temperature!
37 64
59oC 81oC 59oC 37

1
1
10oC/W
10 C/W
o
34 34
32oC 36oC 33
32oC

0oC

16
High Temperatures

Place Thermal Vias

17
High Thermal Gradients

Place Thermal Vias

18
 Impractical to place thermal vias individually
 Use arrangement of thermal vias instead
 Gives thermal via density value
 Changes the effective thermal conductivity
Thermal Via Region
High Thermal Via Density

High Effective Thermal Conductivities

19
 High Thermal Gradients

High Thermal Via Density

High Thermal Conductivity

20
 Old Temperatures

Thermal
Gradients
Thermal Conductivities

New Temperatures

21
 Initial Temperatures

Thermal
Gradients
Thermal Conductivities

New Temperatures

Thermal Via Densities

22
 P
Mathematical Formulation
 Heat transfer within an element (region) K
 K ∆T=P
∆T
 Assume P doesn’t change between iterations
 Knew ∆Tnew = Kold ∆Told
 Knew = Kold (∆Told / ∆Tnew)
 Using the thermal gradient, g = ∆T /d,
 Knew = Kold (gold / gnew)
 Let gnew slowly approach an ideal value, gideal
 gnew = gideal (gold / gideal )α, 0 ≤ α ≤ 1
 Knew= Kold (gold / gideal )1- α
 Update gideal using maximum temperature
 gideal = gideal (Tmaxideal / Tmax)
23
 Thermal Via Placement Algorithm
GIVEN IDEAL MAXIMUM TEMPERATURE: Tmaxideal

SET K’s TO MINIMUM AND CALCULATE THERMAL PROFILE

FOR EACH THERMAL VIA REGION

UPDATE Kz= Kz (g / gideal )1- α

UPDATE m and Klateral

Main loop

CALCULATE THERMAL PROFILE

UPDATE gideal = gideal Tmaxideal /Tmax

CONVERGED?
NO
YES
DONE

24
Thermal Conductivities of Thermal Via Regions
The Relations hip between Therm al Via Dens ity and Therm al Conductivity

V e rtic a l th e rm a l c o n d u c tiv ity

L a te ra l th e rm a l c o n d u c tiv ity

6 300.00

5 250.00

4 200.00

3 150.00

2 100.00

1 50.00

0 0.00
0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50%
Percent Metallization

Layer Interlayer
Thermal
Thermal Conductivity Percent Percent
Conductivity
Thermal Via Thermal Via
Lateral Vertical Lateral Vertical
Minimum 2.15 1.11 0 1.10 1.10 0
Midrange 3.21 100.33 25 1.31 50.71 12.5
Maximum 5.75 199.55 50 1.65 100.33 25 25
Range of Temperature Values
Thermal Via Density of Thermal Vias Regions
Benchmark Circuit
Minimum (0%) Midrange (23.9%) Maximum (47.9%)
name cells Tave Tmax Tave Tmax Tave Tmax
struct 1888 15.4 58.9 10.9 35.0 10.4 31.3
biomed 6417 14.6 46.0 10.5 24.1 10.0 20.2
ibm01 12282 14.2 45.1 10.1 26.2 9.6 22.7
ibm04 26633 13.5 54.0 10.0 26.5 9.6 21.4
ibm09 51746 13.8 53.0 10.2 26.8 9.8 21.4
ibm13 81508 14.6 47.3 10.3 23.6 9.7 19.3
ibm15 158244 15.1 52.8 10.5 26.5 9.9 20.6
 Midrange thermal via densities produce
 47.1% lower maximum temperatures
 28.3% lower average temperatures

26
Range of Temperature Values
Thermal Via Density of Thermal Vias Regions
Benchmark Circuit
Minimum (0%) Midrange (23.9%) Maximum (47.9%)
name cells Tave Tmax Tave Tmax Tave Tmax
struct 1888 15.4 58.9 10.9 35.0 10.4 31.3
biomed 6417 14.6 46.0 10.5 24.1 10.0 20.2
ibm01 12282 14.2 45.1 10.1 26.2 9.6 22.7
ibm04 26633 13.5 54.0 10.0 26.5 9.6 21.4
ibm09 51746 13.8 53.0 10.2 26.8 9.8 21.4
ibm13 81508 14.6 47.3 10.3 23.6 9.7 19.3
ibm15 158244 15.1 52.8 10.5 26.5 9.9 20.6
 Midrange thermal via densities produce
 47.1% lower maximum temperatures
 28.3% lower average temperatures

27
 Results
Thermal Via Regions
Benchmark Tave Tmax Run Time
Circuit Kave % thermal via (sec)

struct 34.9 8.5% 11.4 35.0 3.9

biomed 50.1 9.2% 10.9 24.1 18.2
ibm01 57.1 14.1% 10.1 26.2 19.1
ibm04 51.6 12.7% 10.1 26.5 43.1
ibm09 51.1 12.6% 10.3 26.8 61.5
ibm13 59.8 14.8% 10.3 23.6 134.0
ibm15 45.9 11.3% 10.8 26.5 191.5
 Same maximum temperatures as with midrange via densities
 1.8% higher average temperatures
 11.9% thermal via density in thermal via regions (1.2% in chip)
 50.3% lower than the midrange value
28
 Results
Thermal Via Regions
Benchmark Tave Tmax Run Time
Circuit Kave % thermal via (sec)

8.5% 11.4 35.0

struct 34.9 3.9
(-64.4%) (4.6%) (0.02%)
biomed 50.1 9.2% 10.9 24.1 18.2
ibm01 57.1 14.1% 10.1 26.2 19.1
ibm04 51.6 12.7% 10.1 26.5 43.1
ibm09 51.1 12.6% 10.3 26.8 61.5
ibm13 59.8 14.8% 10.3 23.6 134.0
ibm15 45.9 11.3% 10.8 26.5 191.5
 Same maximum temperatures as with midrange via densities
 1.8% higher average temperatures
 11.9% thermal via density in thermal via regions (1.2% in chip)
 50.3% lower than the midrange value
29
Before Thermal Via Placement

30
After Thermal Via Placement

31
 Conclusions
 Thermal vias have a greater effect in 3D ICs
 Thermal via regions provide regularity
 Efficient iterative method
 Uses thermal gradients to adjust thermal conductivities

 Ideal maximum temperature

 Use lowered value as an objective

 Minimizes use of thermal vias

 Vias are put where they make the most impact

 Reduces thermal resistance on heat conduction paths

32