Lecture #43

OUTLINE
• Short-channel MOSFET (reprise)
• SOI technology

Reading: Finish Chapter 19.2

Spring 2007 EE130 Lecture 43, Slide 1

 Short-Channel MOSFET
OUTPUT CHARACTERISTICS TRANSFER CHARACTERISTICS
0.4
L = 0.15 m
V gs = 2.5V
Vt = 0.4 V
0.3
I ds (mA/m)

V gs = 2.0V

0.2
V gs = 1.5V

0.1 V gs = 1.0V

0.0
0 1 2 2.5
V ds (V)
0.03 • IDS does not saturate with increasing VDS due to DIBL, and also
2.0 m
L =channel-length Vgs = 2.5 V
modulation for VDS>VGS-VT
Vt = 0.7 V

0.02
Spring 2007 EE130 Lecture 43, Slide 2
)
 Silicon on Insulator (SOI) Technology

TSOI

• Transistors are fabricated in a thin single-crystal Si

layer on top of an electrically insulating layer of SiO2
 Simpler device isolation  savings in circuit layout area
 Low junction capacitances  faster circuit operation
 Better soft-error immunity
 No body effect
 Higher cost

Spring 2007 EE130 Lecture 43, Slide 3

 Partially Depleted SOI (PD-SOI)
2 s (2F )
TSOI  WT , where WT 
qN body
Floating body effect (history dependent):
1. When a PD-SOI NMOSFET is in the ON state, at
moderate-to-high VDS, holes are generated via impact
ionization near the drain
2. Holes are swept into the neutral body, collecting at the
source junction
3. The body-source pn junction is forward biased
4.  VT is lowered  IDsat increases
 “kink” in output ID vs. VDS curve

Spring 2007 EE130 Lecture 43, Slide 4

 Fully Depleted SOI (FD-SOI)
2 s (2F )
TSOI  WT , where WT 
qN body

• No floating body effect!

• VT is sensitive to SOI film thickness
• Poorer control of short-channel effects due to fringing
electric field from drain
Gate
• Elevated S/D contact structure Source SOI Drain
needed to reduce RS, RD
SiO2

Silicon Substrate

Spring 2007 EE130 Lecture 43, Slide 5