EMT 235 DIGITAL ELECTRONIC PRINCIPLES 2

MEMORY BASICS

SITI ZARINA BINTI MD NAZIRI | SCHOOL OF MICROELECTRONIC ENGINEERING (SoME)

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(Edited from previous slides by Norina Idris, SoME)
 A General Purpose Processor

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 Memory ???
 A major component of a digital computer and many digital
systems.

 Stores binary data, either permanently or temporarily.

 Consists of arrays of elements: latches, capacitors or MOS

transistors.

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 Overview
 Memory definitions
 Random Access Memory (RAM)
 Static RAM (SRAM) integrated circuits
 Cells and slices
 Cell arrays and coincident selection
 Arrays of SRAM integrated circuits
 Dynamic RAM (DRAM) integrated circuits
 DRAM Types
 Synchronous (SDRAM)
 Double-Data Rate (DDR SRAM)
 RAMBUS DRAM (RDRAM)
 Arrays of DRAM integrated circuits

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 Memory Definitions
 Collection of cells capable of storing binary information.
 Contains electronic circuits for storing & retrieving
information.
 Used to provide temporary or permanent storage capability.
 Semiconductor memories consists of arrays of elements that
are generally latches, capacitors or MOS transistors.

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 A 64-cell memory array organized in 3 different ways

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

6 Digital Fundamentals, 8e Upper Saddle River, New Jersey 07458
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 Memory Address and Capacity
 Each memory location needs an address.

 If the memory is addressed to a cell, then one bit is

addressed.
 But, if the memory is addressed to the Byte or Word,
then that is the smallest amount of data that can be
addressed.

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Examples of memory address

Bit/Cell
Addressing

Byte/Word/
Row
Addressing

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

8 Digital Fundamentals, 8e Upper Saddle River, New Jersey 07458
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 Example of memory address in 3-D array

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 Memory Units
 Bit : a single binary digit.

 Nibble : a group of 4 bits accessed together.

 Byte : a group of 8 bits accessed together.

 Word : a group of binary bits whose size is a

typical unit of access for the memory. (e.g., 1 byte,
2 bytes, 4 bytes, 8 bytes, etc.)

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 Memory data elements
 Memory Data
 A bit or a group of bits to be stored into or
accessed from memory cells.

 Memory Operations
 Operations on memory data supported by the
memory unit. Typically, read and write
operations over some data element (bit, byte,
word, etc.).
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 Basic Memory Operations
 Write operation

 Puts data into a specified address in memory.

 Read Operation
 Takes data out of a specified address in memory.

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 Block Diagram of a Memory Unit

Bidirectional

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 Note the separate Row and
3-D Memory Array Column address decoders…

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 The ‘Write’ operation

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 The ‘Read’ operation

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 Types of Memories
 Random Access Memory (RAM)
 Write operation – stores new info.
 Read operation – transfer the stored info out of
memory.
 Volatile

 Read Only Memory (ROM)

 Performs the Read operation only
 Non-volatile
PROM, EPROM, EEPROM, uv-EPROM
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 RAMs
 RAM – (Random-access memory)

 Data can be written into or read from any selected

address in any sequence.
 When writing, original data in the cell address is replaced with
new data.
 When reading, the cell data remains there.

 RAM lose of stored data when power is turned off –

volatile memories.

 Usually used for short-term data storage.

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 ROMs
 ROM – (Read-only memory)
 Data is stored permanently or semi-permanently.
 Data is read but a write operation as in a RAM memory is
also possible with special equipment.
 Still random access like RAM, but ROMs retain data even
when power is turned off.

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 Memory Basic Process
 Info/content from memory is sent to h/w (usually consists
of registers & combinational logic) to be processed.
 The processed info is then returned to the same or different
memory address.
 Input and Output devices may also interact with memory.

Printers
Mouse
Keyboard
Monitor Hardware
Digital Camera
Scanners
I/O Memory for
Plotters processing
Thumb Drive
External Memory

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 Calculator Exercise
2 8  256
 2 12  4,096

 2 16  65,536
 2 24  16,777,216
 2 32
 4,294,967,296

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 Memory Organization
 Organized as an indexed array of words. Value of the index
for each word is the memory address.
 Often organized to fit the needs of a particular computer
architecture. Some historically significant computer
architectures and their associated memory organization:
 Digital Equipment Corporation PDP-8 (DEC Alpha)
 used a 12-bit address to address 4096 12-bit words.
 IBM 360
 used a 24-bit address to address 16,777,216 8-bit words, (or
4,194,304 32-bit words).
 Intel 8080 (8-bit predecessor to the 8086 and the current
Intel processors)
 used a 16-bit address to address 65,536 8-bit (bytes).

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 Address bus width vs No. of Memory
words
Address bus width No. of memory words

12 bits 4,096 bits

16 bits 65,536 bits

24 bits 16,777,216

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 Memory Block Diagram
A basic memory system is
shown here:

 k address lines are decoded to

address 2k words of memory.

 Each word is n bits.

 Read and Write are single

control lines defining the
simplest of memory
operations.

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(Refer to next slide for example)
 Memory Organization

Example of memory contents above:

• No. of data bits = 8; n = 8
• No. of address bits = 3; k = 3
• Therefore the number of address lines = m = (2k); 23 = 8
• Address range: 0 to 2k -1; therefore 0 to 23 – 1, Add. Range: 0 to 7
• 1 word is the size of the memory content; so the memory above
25 has 8 words of 8-bit data
 The ‘Write’ operation
No. of columns =
k=3 No. of Data bits
n = No. of Data input
& output lines

n=8

No. of add. Rows

(locations)
m = 2k = 8 n-bits per word
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 Memory Size

No. of words x Data width

No. of address lines No. of bits per word

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 Memory Size Units
 K (Kilo) = 210

 M (Mega) = 220

 G (Giga) = 230

Examples :
 64K = 216 = (26 * 210)
 2M = 221 = (21 * 220)

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 4G = 232 = (22 * 230)
 Memory Organization Example
• Address bits = k = 10.
• Address lines = (2k)
210 = 1024 or 1K, labeled
0 to 1023.
• Data bits =16; n = 16.
• Memory content = 16-bit.
• Memory Capacity is 1K
words of 16-bits each, or
“1K x 16-bits”.

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 Memory Operations
 Memory operations require the following:
 Data
 Address
 An operation ─ Typical operations are READ and WRITE. (RAM)

 Read Memory ─ an operation that reads a data value stored in memory: (takes
from memory)
 Place a valid address on the address lines
 Activate the Read input.
 Note : the content of the selected word are not changed by reading them

 Write Memory ─ an operation that writes a data value to memory:

 Place a valid address on the address lines
 Apply data on the data lines
 Activate the Write input

 Other than Read/Write (R/W) Chip Select is used to enable a

particular RAM. It is sometimes called Memory Enable.
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 Memory Enable

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 Exercise Questions
1. How many address lines and data lines are needed for each
of the following memories?

 16K x 8
 256K x 16
 64M x 32
 2G x 8

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 … Exercise Questions
2. Sketch the memory organisation for each of the following
memories.

 16K x 8
 256K x 16
 64M x 32
 2G x 8

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 … Exercise Questions
3. Give the no. of bytes stored in each of the following
memories.

 16K x 8
 256K x 16
 64M x 32
 2G x 8

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 ROM

Read Only Memory

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The ROM family

36 Thomas L. Floyd
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e
All rights reserved.
ROM cells

37 Thomas L. Floyd
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e
All rights reserved.
A representation of a 16 x 8-bit ROM array

38 Thomas L. Floyd
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e
All rights reserved.
MOS PROM array with fusible links

39 Thomas L. Floyd
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e
All rights reserved.
Ultraviolet erasable PROM (EPROM) package

40 Thomas L. Floyd
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e
All rights reserved.
The storage cell in a flash memory

Uses “Floating Gate” MOS transistor

Example Application: MEMORY STICKs

41 Thomas L. Floyd
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e
All rights reserved.
 RAM

Random Access Memory

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 RAM Integrated Circuit
 Types of random access memory (RAM)
 Static – information stored in latches
 Dynamic – information stored as electrical charges on capacitors
 Charge “leaks” off
 Periodic “refresh” of charge required
 Dependence on Power Supply
 Volatile – loses stored information when power is turned off
(example : FPGA – Flex10K). Both static and dynamic RAM
are volatile.

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 The RAM family

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 SRAM ICs

SRAM = Static RAM

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 Static RAM Cell
 Array of storage cells used to implement static RAM

 Storage Cell Select

 SR Latch
B C
 Select input for S Q
control
 Dual Rail Data C
R Q
Inputs B and B B
RAM cell
 Dual Rail Data
Outputs C and C

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 Static RAM Bit Slice
 Represents all circuitry that is required for 2n 1-bit
Select
words
Word
select
0
B
XC
 Multiple RAM cells S Q
Word
C
X select
 Control Lines:
B R Q
RAM cell 0
RAM cell

 Word select i Word

select
1
– one for each word Word Select RAM cell
select
2n 1
 Re ad / Write Word
S Q X
select
 Bit Select 2n 1
RAM cell
R Q X

 Data Lines: RAM cell

Read/Write
logic
 Data in Data in
S Q Data out
 Data out Data in Read/ Bit
Write select
R Q
(b) Symbol

n here is previously mentioned Write logic Data out

47 as “k” Read/
Write
Bit
select
Read logic

(a) Logic diagram

 2n-Word  1-Bit RAM IC
4-to-16 Word select
Decoder 0
 To build a RAM IC A3 A3 23 1
2 RAM cell
from a RAM slice, A2 A2 22 3
4
we need: A1 A1 21 5
6 RAM cell

 Decoder decodes A0
16 x 1
A0 20 7
8
RAM
the n address lines to 9
10

2n word select lines Data

input
Data
output
11
12
13
 A 3-state buffer 14
Read/ 15
 on the data output Write
RAM cell
permits RAM ICs to Memory
enable

be combined into a (a) Symbol Read/Write

logic

RAM with c  2n Data input Data in

Data
words Data out
Read/ Bit
output
Write select

Read/Write
48 n here is previously mentioned as “k” Chip select
(b) Block diagram
 RAM : Cell Arrays and Coincident
Selection
 Memory arrays can be very large =>
 Large decoders
 Large fanouts for the bit lines
 However, the decoder size and fanouts (outputs) can be reduced by
using a coincident selection in a 2-dimensional array:
 Uses two decoders, one for words and one for bits
 Word select becomes Row select
 Bit select becomes Column select

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 Coincident… ??

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 Previous 16 x 1 RAM

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Coincident Selection Approach for the 16 X 1 RAM Chip

• 4 bit address [A3..A0] thus

24 = 16 RAM cells

• The column decoder is

enabled with the CS input

• When CS =0, column

decoder is disabled and all
o/p’s are 0 and NONE of
the cells are selected

 A3 and A2 used for

Row select

 A1 and A0 for
Column select

52 16 X 1 RAM using
4 X 4 RAM Cell Array
 Coincident Selection Approach
If Address is 1001:
• A3, A2 = 10, row decoder
line 2 active
• Activating RAM 8,9,10 & 11

• A1, A0 = 01, column

decoder line 1 active
• Activating RAM 1,5,9,13

• The intersect RAM, RAM

9, is activated. Other
RAM cells not selected
are disabled.
• Then it depends on the
operation functions (Read
or Write)
• Read : Data out thru OR
gate and tri-state buffer
• Write : Data available on
the Data input line is
transferred into the 4x4 RAM Cell Array
selected RAM cell.
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 Constructing RAM
 Previously : Block Diagram of a 16 X 1 RAM using 4 X 4
RAM Cell Array.

 How to create 8 X 2 RAM using 4 X 4 RAM Cell Array?

 Number of Address bits = 3-bits (8 = 23)

 Number of Data bits = 2-bits

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 cauTioN … do NoT geT conFuSed…
MEMORY SIZE ARRAY SIZE

 16K x 8  16 X 1

 256K x 16  4X4
VERSUS
 64M x 32  8X2

 2G x 8

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3-bits addressing
• 2-bits at Row Decoder
• 1-bit at Column Decoder

Since 2 bits at a time are

to be written or read:
2 input lines
• Data input 0
• Data input 1
2 output lines
• Data output 0
• Data output 1

Example:
If Address is = 011
Row Decoder = line 1
RAM = 4,5,6 & 7

Column Decoder = line 1

RAM = 2,6,10,14 and
3,7,11,15

Therefore
56 : Cells 6 & 7 Construct 8x2 RAM using 4x4 RAM cell array
are activated
 Constructing other RAM sizes…
 How about the 32K X 8 bit?

 No. Address bits = 15-bits (32 x 210 = 25 x 210)

 No. Data bits = 8

 Without Coincident selection a single decoder

would have 15 inputs and 32,768 outputs. (32 x 1K =
32 x 1024)
 And 32,800 no of gates.

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 … Constructing RAM
 With Coincident selection:
 Make row and column equal
 Total no. of RAM cells = 32K x 8 = 256K = 262,144
 Take Square Root of 262144 = 512
 (No. columns = No. Rows)
 512 = 29 , meaning 9-bits is fed to the ROW Decoder.
 Remaining 6-bits is fed to the COLUMN Decoder.
 Row Decoder : 9 to 512 line decoder
 Column Decoder : 6 to 64 line decoder
 No of gates = 608

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