COMPUTER ARCHITECTURE

ASSIGNMENT PRESENTATION ON DESIGN OF

BASIC COMPUTER

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 PRESENTED BY

 DEEPAK. A 17E110
 DEEPANA.M 17E111
 DHAMODHAR.R.V 17E112
 DHIVYA.S 17E113
 DINESH KIRUTHIK.K. 17E114
 ELAKIYA.M 17E115
 HARIHARAN.S 17E116

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 CONTENTS
 Hardware components
 Flowchart for computer operation
 Control logic gates
 Control of registers and memory
 Control of single flipflop
 Control of common bus
 Design of accumulator logic
 Control of ac register
 Adder and logic circuit

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 HARDWARE COMPONENTS
 Memory unit – 4096 words of 16 bits each.
 9 registers-AR,PC,DR,AC,IR,TR,OUTR,INPR,SC
 7 flipflops-I,S,E,R,IEN,FGI,FGO
 2 decoders
# 3*8 operation decoder
# 4*16 timing decoder
• 6 bit common bus
• Control logic gates
• Adder and logic circuit connected to input of AC.

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  Memory unit- commercial source
 Registers – integral circuit type 74163
 Flipflops-D or Jktype
 2 decoders- n to m line decoders (m<=2n)
 Common bus system – sixteen 8*1 multiplexer

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 CONTROL LOGIC GATES

 Inputs to the circuit-2

decoders
*I flipflop
*0 to 11 bits of IR
Other inputs
- AC bits 0 to 15( to check
if AC=0 , to detect sign bit
in AC(15)
- DR bits 0 to 15 ( to
check if DR=0 , values of 7
ff)

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 CONTROL LOGIC GATES
Outputs of control logic circuit
 Signals to
control inputs of 9 registers
control read and write inputs of memory
set , clear or complement the ff
S2 S1 and S0 to select a register for the bus
control AC adder and logic circuit.

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 CONTROL OF REGISTERS AND MEMORY
 Registers of computer are connected to common bus system
 Control inputs of registers – LD( load),INR(increment) and CLR
( clear)
 Statements that change the content of AR

 1st 3 statements-transfer info from register / memory to AR

 Content(source register)busAR by enabling its LD
 4th statement clears AR to 0
 Last statement increments AR by I
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  Control functions can be
combined into 3 boolean
expressions

 LD(AR) - load input of AR

 CLR(AR) - clear input of
AR
 INR(AR)- increment input
of AR

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  Control gates for other registers as well as the logic needed
to control the read and write inputs of memory
 Logic gates- read input of memory is derived by scanning the
circuit to find statements that specify read operation.

 O/P of logic gate – implement boolean expression must be

connected to read input of memory.

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 CONTROL OF SINGLE FLIPFLOP
 IEN(interupt flag which can be enabled or disabled) may
change as a result of 2 instructions ION and IOF.
pB7 : IEN1
pB6: IEN0
Where p=D7IT3 and B7 and B6 – bits 7 , 6 of IR,resp.
At end of interupt cycle IEN is cleared to 0.
RT2: IEN0

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 CONTROL OF COMMON BUS
 16 bit common bus- controlled by selection inputs S0 S1 and
S2
 binary number associated with a boolean variable x1
through x7 – gate structure– active in order to select the
register or memory for the bus.

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  When x1 = 1,value S0S1S2 must be 001, o/p of AR will be
selected for the bus.
 the truth table resembles binary encoder
 placement of encoder @ i/p of bus selection logic is shown.

 Logic for each encoder i/p , we need to find control function

that place the corresponding register onto the bus.

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  Data o/p from memory are selected for bus when x7 = 1 and
S2S1S0 = 111
 gate logic that generates x7 must also be applied to input of
memory.
 Boolean expression for x7 for read operation

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 DESIGN OF ACCUMULATOR LOGIC
 The adder and logic circuit has three sets of inputs.
*One set of 16 inputs comes from the outputs of AC.
*Another set of 16 inputs comes from the data register.
*Third set of eight inputs comes from input register INPR.
The output of adder and logic circuit provide data inputs for
register.
Logic gates for controlling the LD, INR, and CLR in registers.

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 CONTROL OF AC REGISTER

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 CONTROL OF AC REGISTER

 The gate structure controls the LD, INR, and CLR inputs of
AC.
 The gate configuration derived from the control functions.
 The control functions for clear microoperation is rB11, where
r=D7I’T3 and B11=IR(11).
 Output of the AND gate generates this control function is
connected to the CLR input of the registers.

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 ADDER AND LOGIC CIRCUIT

 Output of gate implements the increment microoperation is

connected to the INR input of the register.
 The other seven microoperation generated in adder and
logic circuit and loaded into AC at proper time.
 Outputs of gates for each control function is marked with a
symbolic name.
 These outputs are used in the design of the adder and logic
circuits.

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 GATE STRUCTURE FOR CONTROLLING
THE LD,INR,AND CLR OF AC

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 ADDER AND LOGIC CIRCUIT
• Adder and logic circuit can be subdivided into 16
stages,each
• stage corresponding to one bit of ac .
• Each stage has a JK flip flop, two OR gates, and two AND
• gates.
• The load input is connected to inputs of AND gates.
• The input is labled Ii and output AC (i)
• When the LD input is enabled ,16 inputs Ii
• for i=0,1,2,3,4,…….,15 are transferred to AC(o-15)
• One stage of the adder and logic circuit consist of seven
AND gates one OR gates and full adder .

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  The input of the gates with symbolic names come from the
output of gates marked with same symbolic name .
 For example:The input marked ADD is connected to the
output marked .
 The AND operation is achieved by ANDing AC (i) with the
corresponding bit in the data register DR (i)
 The ADD operation is obtained using a binary adder
 Once stage of the adder uses a full adder with the
corresponding input and output carries./

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  The transfer from INPR to AC is only for bits 0 through 7.
 The complement microoperation is obtained by inverting the
bit value in AC.
 The shift right operation transfers the bit from AC(i+1)
 And the shift left operation transfers the bit from AC(i-1)
 The complete adder and logic circuit consists of 16 stages
connected together.

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 THANK YOU

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