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Lec 3
MOS Transistor I
A D I
VB
Important derived parameters. With VG = VB = 0:
• F – Buck Fermi Potential (Substrate)
• S – Surface Potential (Substrate)
2 S i S F
x d
qNA
4 CMOS Digital Integrated Circuits
MOS Transistor Basics
Two Terminal Structure (Continued)
Q q N A x d 2q N A S i s F
Note that this density is per unit of area.
With VG>0 and larger, VB=0, Inversion – A n-type inversion layer forms,
a condition known as surface inversion. The surface is inverted when the
density of electrons at the surface equals the density of holes in the bulk.
This implies that s has the same magnitude but opposite sign to F. At the
point depletion depth fixed and the maximum depletion region depth is at
s = -F. This depth is:
2 S i 2 F
xdm q N A
Q0 q N A xd 2q N A S i 2 F
The inversion phenomena is the mechanism that forms the n-channel. The
depletion depth and the depletion region charge are critical in determining
properties of MOSFET.
p-Substrate
The MOS n-channel transistor structure:
G(ate)
S(ource) D(rain)
n+ L n+
D D D D S
B G
G G G G
S S S S D
N-channel (for P-channel, reverse arrow or add bubbles)
P-channel
Enhancement mode: no conducting channel exists at VGS = 0
Depletion mode: a conducting channel exists at VGS = 0
D VDS
B
G
VSB
VGS S
Q 2q N A S i 2 F V SB
2q N A Si
C ox
The final expression for VT0 and VT are
QB 0 Qox
V T 0 GC 2F
Cox Cox
and
VT VT0 2F VSB 2F
• The threshold voltage depends on the source-to-bulk voltage which
is clearly separated out. The component is referred to as body
effect. If the source to body voltage VSB is non-zero, the corrective
term must be applied to VT0.
D D D D
B
G G G G
S S S S
gate
gate
current
source drain VDS < VGS – VT0
IDS
gate
current
source drain VDS = VGS – VT0
IDS
gate
source drain
VDS > VGS – VT0
IDS
VS=0 VDS<VDSAT
VGS>VT0
Oxide
VB=0
xl
Drain end
dy
Channel
Source end
22 CMOS Digital Integrated Circuits
Gradual Channel Approximation
Linear Mode (Cont.)
• The differential resistance (dR) of the channels can represented in
terms of the mobile electron charge (QI (y)) in the surface
inversion layer, and the electron surface mobility μn (about ½ of
the bulk electron mobility)
dy dy dy
dR
n An q n N AWx d ( y ) W n Q I ( y )
ID
dV c I D dR dy
W n Q I ( y )
xd
Drain end
dy
Channel
Source end
23 CMOS Digital Integrated Circuits
Gradual Channel Approximation
Linear Mode (Cont.)
• Integrating the Ohm’s Law equality between the differential voltage
in the channel and the differential resistance times the drain current,
L
I D dy W n 0 QI ( y ) dV c
V DS
I D L W n C ox 0 V GS V c V T 0 dV c
V DS
xd
Drain end
dy
Channel
Source end
24 CMOS Digital Integrated Circuits
Gradual Channel Approximation
Linear Mode (Cont.)
• Finally, the drain current is
n C ox W
I D ( lin) 2(V GS V T 0 )V DS V 2DS
2 L
• To simplify the equation, we define
W W
' n C ox
L L
κ’: the process transconductance parameter
κ: the device transconductance parameter
n C ox W
I D ( SAT ) (V GS V T 0 )2
2 L
5
VGS= 2.5 V
Resistive Saturation
4
VGS= 2.0 V
ID (A)
3 Quadratic
VDS = VGS - VT Relationship
2
VGS= 1.5 V
1
VGS= 1.0 V
0
0 0.5 1 1.5 2 2.5
VDS (V)
Oxide
0 y L’ ΔL L
(p+) Source Drain (p+)
n+ n+
Channel Pinch-off point (Q =0)
I
Depletion region
Substrate (p-Si)
VB=0
1 V DS
1 1 1 1 1 1 1 1 1
L' L ΔL L L ΔL L 1 ΔL L 1 V DS L
L L
λ: channel length modulation coefficient
ID(SAT) can be rewritten as
n C ox W
I D ( SAT ) (V GS V T 0 )2 (1 V DS )
2 L
nMOS
Mode ID Voltage Range
Cut-off 0 VGS<VT
Linear (μnCox/2)(W/L)[2(VGS-VT)VDS-VDS2] VGSVT,VDS< VGS -VT
Saturation (μnCox/2)(W/L)(VGS-VT)2(1+λVDS) VGS VT,VDS VGS -VT
pMOS
Cut-off 0 VGS>VT
Linear (μnCox/2)(W/L)[2(VGS-VT)VDS-VDS2] VGS VT,VDS> VGS -VT
Saturation (μnCox/2)(W/L)(VGS-VT)2(1+λVDS) VGS VT,VDS VGS -VT
32 CMOS Digital Integrated Circuits
More Parameter Extraction
• Using the intercept of the line for VSB nonzero, the body effect
coefficient γ can be found
V T V SB V T 0
2 F V SB 2 F
F can be obtained from the substrate acceptor density NA and
other known physical constants
ID
VDS = VGS VSB = 0 VSB > 0
ID
VSB Slope = n / 2
VGS
VT0 VT1
34 CMOS Digital Integrated Circuits
More Parameter Extraction (Cont.)
ID
VDS
VDS1 VDS2
• The Level 1 model is valid only for long devices and is obsolete
for most of today’s technologies for detail simulation.
• Parameter extraction for more advanced models such as Level 3 or
4 is usually performed by an automatic parameter extraction
system that optimizes the combined parameter values for a best
non-linear fit to the I-V curves.
• Due to this optimization, derivation of Level 1 model by simply
deleting selected parameters from a Level 3 model is invalided.
Instead, use the Level 3 model to produce I-V curves and linear
curve fitting to extract Level 1 parameters.