NANOELECTRONICS

In this presentation:
- Chip Features
- Fabrication Steps (Cross-section view)
- Testing
- PN Junction Diode
- MOS Capacitor
- pMOS Transistor
- Question Sheet
Chip Features
 1. Alignment Mark 3. Under Pass
2. Bond Pad 4. Scribe Channel

Contact to the
Substrate or
Bulk
10. Ring
Oscillator
5. p-Well
(p-type diffusion)

6. MOS Capacitors
9. (300 μm x 300 μm)
Aluminium
Track
(Common
Source)

8. Transistor or Gate 7. Aluminium Track (Common Gate)

Testing

MOS Capacitor
 Gate Oxide as dielectric
material of capacitor
(SiO2)
Capacitor Gate
(aluminium layer) Contact to Substrate
(n-type silicon)
Capacitance (pF)

Voltage (V)
Capacitance (pF)

+2V Voltage (V)

Dielectric Layer(s)
Capacitance (pF)

+1V Voltage (V)

Dielectric Layer(s)
Capacitance (pF)

0V Voltage (V)

Dielectric Layer(s)
Capacitance (pF)

-1V Voltage (V)

Dielectric Layer(s)
Capacitance (pF)

-2V Voltage (V)

Dielectric Layer(s)
Capacitance (pF)

-3V Voltage (V)

Dielectric Layer(s)
Capacitance (pF)

-4V Voltage (V)

Dielectric Layer(s)
Capacitance (pF)

-5V Voltage (V)

Dielectric Layer(s)
Capacitance (pF)

-6V Voltage (V)

Dielectric Layer(s)
Capacitance (pF)

Voltage (V)
Capacitance (pF)

Voltage (V)
 1 1 1 1 1 1
    Ctot  Cox
Ctot Cox Cdep min Ctot Cox Cdep
Threshold
Voltage (Vth)
Capacitance (pF)

Voltage (V)
Capacitance (pF)

2V
Voltage (V)
Capacitance (pF)

1V
Voltage (V)
Capacitance (pF)

0V
Voltage (V)
 Capacitance (pF)

-1V
Voltage (V)
 Capacitance (pF)

-2V
Voltage (V)
 Capacitance (pF)

-3V
Voltage (V)
 Capacitance (pF)

-4V
Voltage (V)
 Capacitance (pF)

-5V
Voltage (V)
 Capacitance (pF)

-6V
Voltage (V)
Capacitance (pF)

Voltage (V)
Capacitance (pF)

Voltage (V)
Testing

PMOS Transistor
All voltages are refered to the SOURCE
Thus: VDS is potential on DRAIN with respect to the SOURCE
VGS is potential on GATE with respect to the SOURCE

Our testing is done with SOURCE and SUBSTRATE at the same potential
The SOURCE and SUBSTRATE is connected to GROUND

Thus: The values of VDS and VGS are the potentials on the drain and gate

Gate Sub.

Drain Source
Gate Voltage = Positive
Gate Voltage = Zero
Gate Voltage = Negative
Question Sheet
Question 1:
Identify the labels 1 through 10 on the layout diagram
Question 1:
Identify the labels 1 through 10 on the layout diagram

1. Alignment Mark
2. Bond Pad
3. Under Pass
4. Scribe Channel
5. P-Well (p-type diffusion)
6. MOS Capacitor (300 um x 300 um)
7. Aluminium Track (Common Gate)
8. Transistor (or gate of the transistor)
9. Common Source
10. Ring Oscillator
Question 2:
What is the function of the small integrated circuit that forms the
top half of the chip? Sketch and label a section taken through an
active transistor and associated pull-up that forms part of the IC.

Ring Oscillator
T
F

F
T T
F F
T T
F F
T T
F F
T T
F

Odd number of inverters

Question 2:
What is the function of the small integrated circuit that forms the
top half of the chip? Sketch and label a section taken through an
active transistor and associated pull-up that forms part of the IC.
Question 2:
What is the function of the small integrated circuit that forms the
top half of the chip? Sketch and label a section taken through an
active transistor and associated pull-up that forms part of the IC.
Question 2:
What is the function of the small integrated circuit that forms the
top half of the chip? Sketch and label a section taken through an
active transistor and associated pull-up that forms part of the IC.

T = -10 Volts and F = 0 Volts

Question 2:
What is the function of the small integrated circuit that forms the
top half of the chip? Sketch and label a section taken through an
active transistor and associated pull-up that forms part of the IC.

T = -10 Volts and F = 0 Volts

Question 2:
What is the function of the small integrated circuit that forms the
top half of the chip? Sketch and label a section taken through an
active transistor and associated pull-up that forms part of the IC.
Question 3:
Compare the Ids characteristics for the six individual transistors
and comment upon them.
Question 3:
Compare the Ids characteristics for the six individual transistors
and comment upon them.

Longer Channel => Less current (Ids)

Wider Channel => More Current
Longer Channel => Flatter curves
Question 4:
What can be inferred from the CV curve of the MOS Capacitor?
Question 4:
What can be inferred from the CV curve of the MOS Capacitor?

Oxide Capacitance (Cox)

Total Capacitance (Oxide and depletion layer)
Threshold Voltage (Vth)
Question 5:
Use the capacitance data to determine the thickness of the thin
oxide (Gate Oxide)
Question 5:
Use the capacitance data to determine the thickness of the thin
oxide (Gate Oxide)

r 0 A
Cox 
tox
Question 6:
Use the capacitance data to determine the maximum width of
the depletion region under the gate oxide
Question 6:
Use the capacitance data to determine the maximum width of
the depletion region under the gate oxide

1 1 1
 
Ctotal Cox Cdepletion
Question 6:
Use the capacitance data to determine the maximum width of
the depletion region under the gate oxide

1 1 1
 
Ctotal Cox Cdepletion

r 0 A
Cdep 
tdepletion
Question 7:
Calculate a value of the surface mobility of holes using any
appropriate data that you have calculated above.
Question 7:
Calculate a value of the surface mobility of holes using any
appropriate data that you have calculated above.

0 C( ox per unit area ) W

I ds  (Vgs  Vth ) 2

2L
Recommended Reading
- PN Diodes
- MOS Capacitors
- MOS CV Curves
- PMOS Transistors
- PMOS Inverters