Register Transfer Level Design With Verilog: Verilog Digital System Design Z. Navabi, Mcgraw-Hill, 2005

Verilog Digital System Design
Z. Navabi, McGraw-Hill, 2005
Chapter 2
Register Transfer Level
Design with Verilog
Prepared by:
Homa Alemzadeh
January 2006 Copyright Z. Navabi, 2006 1
Register Transfer Level Design
with Verilog
2.1 RT Level Design
2.1.1 Control/data partitioning
2.1.2 Data part
2.1.3 Control part
2.2 Elements of Verilog

2.2.1 Hardware modules
2.2.2 Primitive instantiations
2.2.3 Assign statements
2.2.4 Condition expression
2.2.5 Procedural blocks
2.2.6 Module instantiations

Register Transfer Level Design
with Verilog
2.3 Component Description in Verilog
2.3.1 Data components
2.3.2 Controllers
2.4 Testbenches
2.4.1 A simple tester
2.4.2 Tasks and functions
2.5 Summary

RT Level Design
 RT level design:
 Taking a high level description of a design
 Partitioning
 Coming up with an architecture
 Designing the bussing structure
 Describing and implementing various components of the

architecture
 Steps in RT level design:
 Control/Data Partitioning
 Data Part Design
 Control Part Design

RT Level Design
RT Level
Design
Control/data
Partitioning
Data Part Control Part

Control/Data Partitioning
RT Level
Design
Control/data
Control/data
Partitioning
Partitioning

Control/Data Partitioning
RT Level Design
DataPath Control
Reg
Flags & status
Control
Data Inputs
Opcode Outputs
Data flow
Control signals
Control
Data Outputs
Inputs

Data Part
RT Level
Design
Control/data
Partitioning
Data
Data Part
Part Control Part

Data Part
DataPath
Reg
Flags & status
Data Inputs
Opcode
Data flow
Control signals
Data Outputs

Data Part
Output Signals: Going
module DataPath to the control part,
(DataInput, DataOutput, Flags, Opcodes,
provide flags and
ControlSignals); status of the data
input [15:0] DataInputs;

output [15:0] DataOutputs; Control Signals:
output Flags, ...; Inputs to data part,
output Opcodes, ...; sent to the data
input ControlSignals, ...; components and
busses
// instantiation of data components
// ...
// interconnection of data components
// bussing specification
Control Signals for the busses:
endmodule Select the sources and routing
of data from
 DataPath Module one data component
to another
Data Part Data Component:
Shows how the
component uses its
input control
signals to perform
module DataComponent various operations
on its data inputs
(DataIn, DataOut, ControlSignals);
input [7:0] DataIn;

output [7:0] DataOut;
input ControlSignals;
// Depending on ControlSignals
// Operate on DataIn and
// Produce DataOut
endmodule
 Partial Verilog Code of a Data Component

Control Part
RT Level
Design
Control/data
Partitioning

Control Part

Control Part
Control
Flags & status

Control
Opcode Outputs
Data flow
Control signals
Control
Inputs
Makes decisions as
Consists of one or
to when and what
more state machines
control signals to
to keep the state of
issue depending on
the circuit.
its state.
Control Part
module ControlUnit
(Flags, Opcodes, ExternalControls, ControlSignals);
input Flags, ...; Takes control

input Opcodes, ...; inputs from the
input ExternalControls, ...; Data Part
output ControlSignals;
// Based on inputs decide :
// What control signals to issue,
// and what next state to take
endmodule
 Outline of a Controller

Elements of Verilog
 We discuss basic constructs of Verilog language for describing a

hardware module.

Elements of Verilog
Hardware
Modules
Primitive Assign
Instantiations Statements
Condition Procedural
Expression Blocks
Module
Instantiations
Hardware Modules
Hardware
Modules
Modules
Primitive Assign
Expression Blocks
Module
Instantiations
Hardware Modules
module :
The Main
Keyword
Component
module of Verilog
module module-name
Variables, wires, and
List of ports; module parameters
Declarations are declared.
...
Functional specification of module
...
Keyword
endmodule endmodule
 Module Specifications

Hardware Modules
 There is more than one way to describe a Module in Verilog.

 May correspond to descriptions at various levels of abstraction or to
various levels of detail of the functionality of a module.
 Descriptions of the same module need not behave in exactly the same
way nor is it required that all descriptions describe a behavior correctly.
 We discuss basic constructs of Verilog language for a hardware module
description.
 We show a small example and several alternative ways to describe it in
Verilog.

Primitive Instantiations
Hardware
Modules
Primitive
Primitive Assign
Expression Blocks
Module
Instantiations
Logic Gates
called
Primitives
a a_sel
s_bar w
s
b b_sel
 A Multiplexer Using Basic Logic Gates

module MultiplexerA (input a, b, s, output w);

wire a_sel, b_sel, s_bar;
not U1 (s_bar, s);
and U2 (a_sel, a, s_bar); Instantiation
of Primitives
and U3 (b_sel, b, s);
or U4 (w, a_sel, b_sel);
endmodule
 Primitive Instantiations

Assign Statements
Hardware
Modules
Primitive Assign
Expression Blocks
Module
Instantiations
Assign Statements
Continuously
drives w with the
right hand side
expression
module MultiplexerB (input a, b, s, output w);

assign w = (a & ~s) | (b & s);
endmodule
Using Boolean
 Assign Statement and Boolean expressions to
describe the logic

Condition Expression
Hardware
Modules
Primitive Assign
Condition
Expression Blocks
Module
Instantiations
Condition Expression
Can be used when
the operation of a
unit is too complex
to be described by
Boolean expressions
module MultiplexerC (input a, b, s, output w);

assign w = s ? b : a;
endmodule
 Assign Statement and Condition Operator

Very Effective in
describing complex
Useful in describing a functionalities
behavior in a
very compact way

Procedural Blocks
Hardware
Modules
Primitive Assign
Expression Blocks
Module
Instantiations
Procedural Blocks
always
statement Sensitivity list
module MultiplexerD (input a, b, s, output w);

reg w;
always @(a, b, s) begin
if (s) w = b;
else w = a;
end if-else Can be used when the
endmodule statement operation of a unit is
too complex to be
 Procedural Statement described by Boolean or
conditional expressions

Module Instantiations
Hardware
Modules
Primitive Assign
Expression Blocks
Module
Module
Instantiations
module ANDOR (input i1, i2, i3, i4, output y);

ANDOR
assign y = (i1 & i2) | (i3 & i4); module is
endmodule defined
//
module MultiplexerE (input a, b, s, output w);
wire s_bar;
not U1 (s_bar, s);
ANDOR U2 (a, s_bar, s, b, w);
ANDOR
endmodule module is
 Module Instantiation instantiated

a
ANDOR
i1
s i2 y w
i3
b i4
 Multiplexer Using ANDOR

Component Description
in Verilog
Component
Description
Data
Controllers
Components

Data Components
Component
Description
Data
Data
Controllers
Components
Components

Data Components
Data
Components
Multiplexer Flip-Flop
Counter Full-Adder
Shift-Register ALU
Interconnections
Multiplexer
Data
Components
Counter Full-Adder
Shift-Register ALU
Interconnections
Multiplexer
Defines a Time Unit of 1 ns
and Time Precision of 100 ps.
`timescale 1ns/100ps
module Mux8 (input sel, input [7:0] data1, data0,

output [7:0] bus1);
assign #6 bus1 = sel ? data1 : data0;
endmodule
A 6-ns Delay
 Octal 2-to-1 MUX Selects its 8-bit
is specified for all data0 or data1 input
values assigned to depending on its
bus1 sel input.

Flip-Flop
Data
Components
Counter Full-Adder
Shift-Register ALU
Interconnections
Flip-Flop A
Flip-Flops are
Software-Like
used in data part
forProcedural
flags and data
Coding Style
storage
Synchronous
`timescale 1ns/100ps reset input
Flip-Flop The Body of
triggers
module Flop (reset, on the
din, always statement is
clk, qout);
falling edge of Aexecuted
Signal declared
at the as a
input reset, din, clk;
clk Input reg to beedge
negative capable
of of
output qout;
holding its values
the clk signal
reg qout;
between clock edges
always @(negedge clk) begin
if (reset) qout <= #8 1'b0;
else qout <= #8 din;
end
endmodule A Non-blocking
An 8-ns Assignment
 Flip-Flop Description Delay

Counter
Data
Components
Counter Full-Adder
Shift-Register ALU
Interconnections
A 4-bit modulo-16
Counter Counters are used in data
part for registering data,
Counter accessing memory or
queues and register
stacks
4-bit
Register
module Counter4 (input reset, clk,
output [3:0] count);
reg [3:0] count; Constant
always @(negedge clk) begin Definition
if (reset) count <= #3 4'b00_00;
else count <= #5 count + 1;
end When count
endmodule reaches 1111,
the next count
 Counter Verilog Code taken is 10000

Full-Adder
Data
Components
Counter Full-Adder
Shift-Register ALU
Interconnections
Full-Adder
Full-Adders are used
A combinational in data part for
circuit building
Carry-Chain adders
All Changes
Occur after 5 ns
module fulladder (input a, b, cin, output sum, cout);

assign #5 sum = a ^ b ^ cin;
assign #3 cout = (a & b)|(a & cin)|(b & cin);
endmodule
All Changes
Occur after 3 ns
 One
Full-Adder
delay for Verilog Code
every output:
tPLH and tPHL

Shift-Register
Data
Components
Counter Full-Adder
Shift-Register ALU
Interconnections
An 8-bit
2 Mode inputs Shift-Register Universal
Shift Register
m[1:0] form a
`timescale
2-bit number 1ns/100ps
module ShiftRegister8
(input sl, sr, clk, input [7:0] ParIn,
Case Statement
input [1:0] m, output
With 4 reg [7:0] ParOut);
case-alternatives
and default Value
case (m)
m=0 : Does Nothing
0: ParOut <= ParOut;
1: ParOut <= {sl, ParOut [7:1]};
2: ParOut <= {ParOut [6:0], sr}; m=1,2: Shifts Right
3: ParOut <= ParIn; and Left
default: ParOut <= 8'bX;
endcase m=3 : Loads its Parallel
end input into the register
endmodule

Shift-Register (Continued)
module ShiftRegister8
(input sl, sr, clk, input [7:0] ParIn,
input [1:0] m, output reg [7:0] ParOut);
Shift Right:
The SL input is
concatenated to
case (m) the left of
0: ParOut <= ParOut; ParOut
1: ParOut <= {sl, ParOut [7:1]};
2: ParOut <= {ParOut [6:0], sr};
3: ParOut <= ParIn;
default: ParOut <= 8'bX; Shifting the
endcase ParOut to the left
end
endmodule

ALU
Data
Components
Counter Full-Adder
Shift-Register ALU
Interconnections
ALU
module ALU8 (input [7:0] left, right, 2-bit mode Input

input [1:0] mode, to select one of its
output reg [7:0] ALUout); 4 functions
always @(left, right, mode) begin
case (mode)
0: ALUout = left + right;
1: ALUout = left - right; Add
2: ALUout = left & right; Subtract
3: ALUout = left | right; AND
default: ALUout = 8'bX; OR
endcase
end
endmodule
 An 8-bit ALU
ALU (Continued) The Declaration of
ALUout both as
`timescale 1ns/100ps output and reg:
Because of
module ALU8 (input [7:0] left, right, assigning it within
input [1:0] mode, a Procedural Block
output reg [7:0] ALUout);
always @(left, right, mode) begin
case (mode) Blocking
0: ALUout = left + right; Assignments
1: ALUout = left - right;
2: ALUout = left & right;
3: ALUout = left | right;
default: ALUout = 8'bX; default alternative
endcase puts all Xs on ALUOut
end if mode contains
endmodule anything but 1s and 0s
 An 8-bit ALU
Interconnections
Data
Components
Counter Full-Adder
Shift-Register ALU
Interconnections
Interconnections
Inbus Aside Bside
8 8
select_source
Mux8 and ALU 8 8

examples forming a ABinput
Partial Hardware
Function
8
Outbus
 Partial Hardware Using MUX8 and ALU

Interconnections
A Set of parenthesis
Instantiation of enclose port
ALU8 and MUX8 connections to the
instantiated modules
ALU8 U1 ( .left(Inbus), .right(ABinput),

.mode(function), .ALUout(Outbus) );
Mux8 U2 ( .sel(select_source), .data1(Aside),
.data0(Bside), .bus1 (ABinput));
u1 Verilog
and u2 : Code of The Partial Hardware Example
Instance Names

Interconnections
The actual ports
of the instantiated
An Alternative format components
of port connection are excluded
ALU8 U1 ( Inbus, ABinput, function, Outbus );

Mux8 U2 ( select_source, Aside, Bside, ABinput );
 Ordered Port Connection

The list of local signals
in the same order as
their connecting ports

Controllers
Component
Description
Data
Controllers
Controllers
Components

Controllers
Decisions
Based on :Inputs ,
Outputs ,State
Issue Control Signal
Set Next State
Go to Next State
 Controller Outline

Controllers
 Controller:
 Is wired into data part to control its flow of data.
 The inputs to it controller determine its next states and outputs.
 Monitors its inputs and makes decisions as to when and what output
signals to assert.
 Keeps the history of circuit data by switching to appropriate states.
 Two examples to illustrate the features of Verilog for describing state

machines:
 Synchronizer
 Sequence Detector

Controllers
Controllers
Sequence
Synchronizer
Detector

Synchronizer
Controllers
Sequence
Synchronizer
Synthesizer
Detector

Synchronizer
Clk
adata
synched
 Synchronizing adata

Synchronizer
module Synchronizer (input clk, adata,

output reg synched);
always @(posedge clk)
if (adata == 0) synched <= 0; If a 1 is Detected on
else synched <= 1; adata on the rising
endmodule edge of clock,
synched becomes 1
 A Simple Synchronization Circuit and remains 1
for at least one
clock period

Sequence Detector
Controllers
Sequence
Sequence
Synthesizer
Detector
Detector

Sequence Detector
When the sequence
Searches on is detected, the w
it’s a input Output becomes 1
for the and stays 1 for a
110 Sequence complete clock cycle
If 110 is detected
a on a, then w gets w
1, else w gets 0.
clk
 State Machine Description

Sequence Detector
A Moore Machine
Sequence Detector
States are named: The State in which
s0 , s1 , s2 , s3 the 110 sequence is
detected.
0 1
reset
1 1 0
S0 S1 S2 S3
0 0 0 0 1
1
Initia
l 0
State
It Takes at least
3 clock periods to
get to the s3 state
 Sequence Detector State Machine

Sequence Detector
module Detector110 (input a, clk, reset, output w);
parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;
reg [1:0] current;
always @(posedge clk) begin

if (reset) current = s0;
else
case (current)
s0: if (a) current <= s1; else current <= s0;
endcase
end
assign w = (current == s3) ? 1 : 0;
endmodule
 Verilog Code for 110 Detector

Sequence Detector Description
Behavioral
of the
State Machine
module Detector110 (input a, clk, reset, output w);
parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10,

s3=2'b11;
reg [1:0] current; A 2-bit Register Parameter declaration

defines constants
always @(posedge clk) begin s0, s1, s2, s3
if (reset) current = s0;
else
...........................
...........................
 Verilog Code for 110 Detector

Sequence Detector
...........................
...........................
always @(posedge clk) begin if-else statement
if (reset) current = s0; checks for reset
else
At the case (current)
Absence of s0: if (a) current <= s1; else current <= s0;
a 1 on reset s1: if (a) current <= s2; else current <= s0;
endcase
end The 4 Case-alternatives
each correspond to a
 Verilog Code for 110 Detector state of state machine

Sequence Detector
s1 s1:
0
a=1 if (a)
s2 current <= s2;

0
a=0 else
s0 current <= s0;

0
 State Transitions on Corresponding Verilog Code

Sequence Detector
Outside of the
always Block:
A combinational
end circuit
............................
............................
assign w = (current == s3) ? 1 : 0;
Assigns a 1 to w
endmodule output when
Machine Reaches to
 Verilog Code for 110 Detector s3 State

Testbenches
Testbenches
Tasks
A Simple
And
Tester
Functions

A Simple Tester
Testbenches
Tasks
A Simple
And
Tester
Tester
Functions

A Simple Tester
module Detector110Tester;
reg aa, clock, rst;
wire ww;
Detector110 UUT (aa, clock, rst, ww);
initial begin
aa = 0; clock = 0; rst = 1;
end
initial repeat (44) #7 clock = ~clock;
initial repeat (15) #23 aa = ~aa;
initial begin
#31 rst = 1;
#23 rst = 0;
end
always @(ww) if (ww == 1)
$display ("A 1 was detected on w at time = %t", $time);
endmodule
 Testbench for Detector110

A Simple Tester
Begins with
the module
Unlike other
keyword
descriptions
doesn’t have input
`timescale 1ns/100ps or output ports
module Detector110Tester;
reg aa, clock,Outputs
rst; are Inputs are Declared as reg
wire ww; declared as wire
Detector110 UUT (aa, clock, rst, ww);
.........................
......................... The Instantiation of
Detector110 Module

initial statement
drives test values A Simple Tester
into the variables
connected to the An initial statement: A
inputs. sequential statement that
.......................... runs once and stops when
.......................... it reaches its last
initial begin statement
aa = 0; clock = 0; rst = 1;
end
initial repeat (15) #23 aa = ~aa; All Initial Blocks
initial begin Start at Time 0 and
#31 rst = 1; Run Concurrently
#23 rst = 0;
end

A Simple Tester
Repeats 44 times of
.......................... complementing the
.......................... For Initializing
clock input with 7ns
the Input Signals
delay, generates a
initial begin
aa = 0; clock = 0; rst = 1; periodic signal
on clock
end
initial repeat (15) #23 aa = ~aa;
initial begin
#31 rst = 1; Signal aa is also
#23 rst = 0; assigned a periodic
end signal, with a
different frequency
Detector110
 Testbench forWaits 31 ns before
assigning 1 to rst

A Simple Tester
always Block
Wakes up when
ww Changes
Reports the
Times at which
..........................
the ww Variable
..........................
becomes 1
always @(ww) if (ww == 1)
$display ("A 1 was detected on w at time = %t",
$time);
endmodule
This Note Will Appear
 Testbench for Detector110 in the Simulation
A Verilog Environment’s
System Task Window: “Console” or
“Transcript”

Tasks And Functions
Testbenches
Tasks
A Simple
And
And
Tester
Functions

Tasks And Functions
 Verilog Tasks and Functions:
 System tasks for Input, Output, Display, and Timing Checks
 User defined tasks and functions
 Tasks:
 Can represent a sub module within a Verilog module
 Begins with a task keyword
 Its body can only consist of sequential statements like if-else and
case
 Functions:
 Can be used for corresponding to hardware entities
 May be used for writing structured codes
 Applications: Representation of Boolean functions, data and code

conversion, and input and output formatting

Summary
 This chapter presented:
 An overview of Verilog and how this language is used for design and
test of RT level description
 Components of an RT level design
 Small examples to illustrate such components and at the same time

Verilog coding of hardware modules
 The descriptions in this part were all synthesizable and had a one-to-
one hardware correspondence.
 How testbenches could be developed in Verilog and new constructs
of it in this part


Register Transfer Level Design With Verilog: Verilog Digital System Design Z. Navabi, Mcgraw-Hill, 2005

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Register Transfer Level Design With Verilog: Verilog Digital System Design Z. Navabi, Mcgraw-Hill, 2005

Загружено:

Авторское право:

Доступные форматы

Verilog Digital System Design

Z. Navabi, McGraw-Hill, 2005

2.2 Elements of Verilog

Verilog Digital System Design

Verilog Digital System Design

 Coming up with an architecture

 Designing the bussing structure

 Describing and implementing various components of the

 Data Part Design

 Control Part Design

Verilog Digital System Design

Data Part Control Part

Verilog Digital System Design

Data Part Control Part

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

input [15:0] DataInputs;

input [7:0] DataIn;

 Partial Verilog Code of a Data Component

Verilog Digital System Design

Data Part Control Part

Verilog Digital System Design

Flags & status

input Flags, ...; Takes control

Verilog Digital System Design

 We discuss basic constructs of Verilog language for describing a

Verilog Digital System Design

Verilog Digital System Design

 There is more than one way to describe a Module in Verilog.

Verilog Digital System Design

Verilog Digital System Design

module MultiplexerA (input a, b, s, output w);

Verilog Digital System Design

module MultiplexerB (input a, b, s, output w);

Verilog Digital System Design

module MultiplexerC (input a, b, s, output w);

 Assign Statement and Condition Operator

Verilog Digital System Design

module MultiplexerD (input a, b, s, output w);

Verilog Digital System Design

module ANDOR (input i1, i2, i3, i4, output y);

Verilog Digital System Design

 Multiplexer Using ANDOR

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

module Mux8 (input sel, input [7:0] data1, data0,

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

module fulladder (input a, b, cin, output sum, cout);

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

module ALU8 (input [7:0] left, right, 2-bit mode Input

Mux8 and ALU 8 8

Verilog Digital System Design

ALU8 U1 ( .left(Inbus), .right(ABinput),

Verilog Digital System Design

ALU8 U1 ( Inbus, ABinput, function, Outbus );

 Ordered Port Connection