Thumb-2 instruction set

• Thumb-2 introduces 32-bit instructions that

are intermixed with the 16-bit instructions.
• The Thumb-2 instruction set covers almost all
the functionality of the ARM instruction set.
• Thumb-2 is backwards compatible with the
ARMv6 Thumb instruction set. Any code that
you have compiled to run on the ARMv6
thumb instruction set runs on the Thumb-2
instruction set.
• The most important difference between the
Thumb-2 instruction set and the ARM
instruction set is that most Thumb-2
instructions are unconditional, where as
almost all ARM instructions can be
conditional.
• However, Thumb-2 introduces a new
conditional execution instruction, IT, that is a
logical if-then-else function.
 The main enhancements are:
• 32-bit instructions added to the Thumb instruction set
to:
– provide support for exception handling in Thumb state
– provide access to coprocessors
– include DSP and media instructions
– improve performance in cases where a single 16-bit
instruction restricts functions available to the compiler.
• Addition of 16-bit Compare and Branch on Zero (CBZ)
and Compare and Branch on Non Zero (CBNZ)
instructions to improve code size by replacing two-
instruction sequence with a single instruction.
Instruction type size instructions
Data operations 16 ADC, ADD, AND, ASR, BIC,
CMN, CMP, CPY, EOR, LSL,
LSR, MOV, MUL, MVN, NEG,
ORR, ROR, SBC, SUB, TST,
REV, REVH, REVSH, SXTB,
SXTH, UXTB, and UXTH.
B<cond>, B, BL, BX, and BLX.
Branches 16 Note, no BLX with
immediate.
LDR, LDRB, LDRH, LDRSB,
Load-store single 16
LDRSH, STR, STRB, STRH.
LDMIA, POP, PUSH, and
Load-store multiple 16
STMIA.
ADC{S}. ADD{S}, CMN,
RSB{S}, SBC{S}, SUB{S}, CMP,
Data operations with
32 AND{S}, TST, BIC{S}, EOR{S},
immediate
TEQ, ORR{S}, MOV{S},
ORN{S}, and MVN{S}.
Instruction type
Data operations with large
32
immediate
Bit-field operations 32
size instructions
MOVW, MOVT, ADDW, and
SUBW.
MOVW and MOVT have a
16-bit immediate. This
means they can replace
literal loads from memory.
ADDW and SUBW have a 12-
bit immediate. This means
they can replace many from
memory literal loads.
BFI, BFC, UBFX, and SBFX.
These are bitwise
operations enabling control
of position and size in bits.
These both support C/C++
bit fields, in structs, in
addition to many compare
and some AND/OR
assignment expressions.
Instruction type size instructions
ADC{S}. ADD{S}, CMN,
RSB{S}, SBC{S}, SUB{S}, CMP,
Data operations with three AND{S}, TST, BIC{S}, EOR{S},
32
registers TEQ, ORR{S}, MOV{S},
ORN{S}, and MVN{S}. No
PKxxx instructions.
ASR{S}, LSL{S}, LSR{S}, RRX
Shift operations 32
{S}, and ROR {S}.
REV, REVH, REVSH, RBIT,
CLZ, SXTB, SXTH, UXTB, and
UXTH.
Miscellaneous 32
Extension instructions same
as corresponding v6 16-bit
instructions.
TBB and TBH table branches
for switch/case use. These
Table branch 32
are LDR with shifts and then
branch.
Multiply 32 MUL, MLA, and MLS.
Instruction type
Multiply with 64-bit result
Load-store addressing
Load-store single
Load-store multiple
Load-store exclusive
size instructions
UMULL, SMULL, UMLAL,
32
and SMLAL.
Supports Format PC+/-
imm12, Rbase+imm12,
Rbase+/-imm8, and
32 adjusted register including
shifts.
T variants used when in
Privilege mode.
LDR, LDRB, LDRSB, LDRH,
LDRSH, STR, STRB, STRH,
32 and T variants. PLD and PLI
are both hints and so act as
a NOP.
32 STM, LDM, LDRD, and STRD.
LDREX, STREX, LDREXB,
32 LDREXH, STREXB, STREXH,
CLREX.
Instruction type size instructions
B, BL, and B<cond>. No BLX (1) because
Branches 32
always changes state. No BXJ.
MSR(2) and MRS(2) replace MSR/MRS but
also do more. These access the other stacks
System 32 and also the status registers.
CPSIE/CPSID 32-bit forms are not supported.
No RFE or SRS.
CPSIE and CPSID are quick versions of MSR(2)
instructions and use the standard Thumb-2
System 16
encodings, but only permit use of i and f and
not a.
NOP (all forms), Coprocessor (MCR, MCR2,
MCRR, MRC, MRC2, and MRRC), and YIELD
Extended32 32
(hinted NOP). Note, no MRS(1), MSR(1), or
SUBS (PC return link).
CBZ and CBNZ (Compare and Branch if
Combined branch 16
register is Zero or Non-Zero).
Instruction type size instructions
Extended 16 IT and NOP. This includes YIELD.
SDIV and UDIV. 32/32 divides both signed and
unsigned with 32-bit quotient result, no remainder,
Divide 32
it can be derived by subtraction. Early out is
permitted.
WFI, WFE, and SEV are in the class of hinted NOP
Sleep 16, 32
instructions that control sleep behavior.
ISB, DSB, and DMB are barrier instructions that
Barriers 32 ensure certain actions have taken place before the
next instruction is executed.
SSAT and USAT perform saturation on a register.
They perform the following:
Normalize the value using shift test for overflow
from a selected bit position, the Q value.
Saturation 32 Set the xPSR Q bit if so, saturate the value if
overflow detected.
Saturation refers to the largest unsigned value or
the largest/smallest signed value for the size
selected.
 List of instructions
• BFC MLS
BFI MOVT
BIC PUSH
CLZ
CLREX POP
LDREX RBIT
STREX REV
SBFX REV16
UBFX SEV
USAT
UXTB REVSH
UXTH WFE
IT WFI
TBB
LDM
STM
MLA