DESIGN OF

LOW POWER
ARITHMETIC LOGIC UNIT
USING
DIODE FREE ADIABATIC
LOGIC
Under the esteemed guidance of Prof. P.V.SRIDEVI
Submitted by:
Devineni Satya Sai (Regd.no:315506507037)
Boni Shanmukh (Regd.no:315506507038)
K.P.S Reddy (Regd.no:315506507042)
Chunduru Sri SriHarsha (Regd.no:315506507043)
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Reduction in energy dissipation is an active area of
research. Systems which consume power require the
deployment of expensive cooling systems.

The main power dissipation in reported adiabatic circuits

in their discharging path occurs at the diodes due to the
threshold voltage drop.

This project implements an ALU circuit that has been

designed in Diode Free Adiabatic Logic(DFAL)
methodology. Two types of ALU circuits are designed, first
by DFAL method, and second one using conventional
CMOS method. The performance of both the ALU circuits
are observed and compared. In the DFAL based ALU
circuit energy efficiency has been improved. An 8-bit ALU
is constructed using the proposed 1-bit ALU.
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The main objective of our project is to design and
implement an ALU circuit which is designed in Diode
Free Adiabatic Logic(DFAL) methodology.

 Two types of ALU circuits are designed, first by DFAL

method, and second one using conventional CMOS
method.

 The performance of both the ALU circuits are

observed and compared.

 In the DFAL based ALU circuit energy efficiency has

been improved.

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A personal computer

Tanner EDA v16.01

180nm CMOS TSMC parameters Library

file

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Complementary metal–oxide semiconductor (CMOS) is a
technology for constructing integrated circuits.

CMOS technology is used

in microprocessors, microcontrollers, static RAM, and
other digital logic.

Diode free adiabatic logic (DFAL),the term “adiabatic” is

derived from a reversible thermodynamic process and it stands
for a system where a transformation takes place in such a way
that no gain or loss of heat/energy occurs.

In this way power dissipation is minimized by decreasing the

peak current flow through the transistors.
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 CMOS based inverter DFAL based inverter

The above mentioned circuits are basic inverter

circuits in CMOS and DFAL.
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The power consumption in conventional CMOS circuits is
proportional to the load capacitance and square of the
supply voltage, thus researchers have been focused on
scaling of the supply voltage and reducing the capacitance
to reduce power consumption.

For scaling the supply voltage, the transistor threshold

voltage (Vt) must also be scaled down proportionally,
however reducing the transistor threshold voltage Vt results
in proportional increase in sub threshold leakage current.

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The main idea in an adiabatic charging is that
transitions are considered to be sufficiently slow so
that all the nodes are charged or discharged at a
constant current. In this way power dissipation is
minimized by decreasing the peak current flow
through the transistors.

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1) NOT GATE (INVERTER):

Inverter based on CMOS Inverter based on DFAL

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CMOS based inverter output waveform

DFAL based inverter output waveform

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2) AND GATE:

EXPRESSION: andOut = a0.b0

CMOS based AND gate DFAL based AND gate

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3) OR GATE:

EXPRESSION: orOut = a0+b0

CMOS based OR gate DFAL based OR gate

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4) EXCLUSIVE-OR GATE:

EXPRESSION: exorOut = a0⊕b0 = a0ꞌb0+a0b0ꞌ

= ((a0ꞌ+b0).(a0+b0ꞌ))ꞌ

XOR gate based on CMOS XOR gate based on DFAL

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5) EXCLUSIVE NOR GATE:

EXPRESSION: exnorOut = a0ʘb0 = (a0⊕b0 )ꞌ

XNOR gate based on CMOS XNOR gate based on DFAL

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OUTPUT WAVEFORMS OF CMOS BASED LOGIC
GATES

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OUTPUT WAVEFORMS OF DFAL BASED LOGIC
GATES

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6) FULL ADDER:

7) FULL SUBTRACTOR:

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OUTPUT WAVEFORMS OF CMOS BASED FULL
ADDER AND FULL SUBTRACTOR

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OUTPUT WAVEFORMS OF DFAL BASED FULL
ADDER AND FULL SUBTRACTOR

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8) 8:1 MULTIPLEXER:

Block diagram of 8:1 multiplexer

TRUTH TABLE OF 8:1 MULTIPLEXER 20/33

• 8:1 MULTIPLEXER CIRCUIT

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OUTPUT WAVEFORMS OF CMOS BASED
8:1 MULTIPLEXER

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OUTPUT WAVEFORMS OF DFAL BASED
8:1 MULTIPLEXER

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9) 1-BIT ARITHMETIC LOGIC UNIT:

(a)Basic Block Diagram Of an 1-Bit ALU (b) Truth Table of 1-Bit ALU

(c) 1-BIT ARITHMETIC LOGIC UNIT 24/33

OUTPUT WAVEFORMS OF CMOS BASED
1-Bit ALU

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OUTPUT WAVEFORMS OF DFAL BASED
1-Bit ALU

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10) 8-BIT ARITHMETIC LOGIC UNIT Using 1-BIT ALU:

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OUTPUT WAVEFORMS OF DFAL BASED
8-BIT ALU
a) Waveforms of a0
to a7

b) Waveforms of
b0 to b7, cin0,bin0.

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(c) Selection line
inputs

(d) Output
waveforms of
DFAL based 8-bit
ALU

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Power dissipation of 1-Bit ALU over different frequencies:

Delay time of 1-Bit ALU over different frequencies:

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Power Delay Product (PDP) of 1-Bit ALU over different
frequencies:

The number of transistors in 1-Bit ALU are

In CMOS based 1-Bit ALU-232.
In DFAL based 1-Bit ALU-291.

The number of transistors in DFAL based 8-Bit ALU are 2328.

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Diode free adiabatic logic (DFAL) family is a novel adiabatic Logic family.
The maximum power dissipation in reported adiabatic circuits in their
discharging path occurs at the diodes where as in DFAL circuits it is due to the
ON resistance of channel of the additional MOS transistor.

The designed circuits are simulated in Tanner EDA simulator using 180nm
CMOS TSMC parameters.

The simulation results and comparative performance evaluation revealed that

power consumption and the overall PDP in the DFAL based ALU is
considerably lower than conventional CMOS based ALU.

The implemented DFAL based ALU outperforms and provides low power
results up to 250MHz.The DFAL based ALU provides almost 46% of energy
saving at 250MHz.

An 8-bit DFAL based ALU is constructed using 1-bit ALU’s and its outputs
are verified. 32/33
PRESENTED BY:

Devineni Satya Sai

(Regd.no:315506507037)
Boni Shanmukh
(Regd.no:315506507038)
K.P.S Reddy
(Regd.no:315506507042)
Chunduru Sri SriHarsha
(Regd.no:315506507043)

THANK YOU !!!!

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