Moore's Law: Electronics, April 19, 1965

LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
© Digital Integrated Circuits2nd

1959
1960
Moore’s Law
1961
1962
Electronics, April 19, 1965.

1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
Inverter
Evolution in Complexity
© Digital Integrated Circuits2nd Inverter

Transistor Counts
1 Billion
K Transistors
1,000,000
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
© Digital Integrated Circuits2nd Courtesy, Intel Inverter

Moore’s law in Microprocessors
1000
100 2X growth in 1.96 years!

Transistors (MT)
10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
Transistors
0.01 on Lead Microprocessors double every 2 years
8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

Die Size Growth
100
Die size (mm)
P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years
1
1970 1980 1990 2000 2010
Year
Die size grows by 14% to satisfy Moore’s Law

Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)
P6
100
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years

Power Dissipation
100
P6
Pentium ® proc
Power (Watts)
10
486
8086 286
386
8085
1 8080
8008
4004
0.1
1971 1974 1978 1985 1992 2000
Year
Lead Microprocessors power continues to increase

Power will be a major problem
100000
18KW
10000 5KW
1.5KW
Power (Watts)
1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive

Power density
10000
Rocket
Power Density (W/cm2)
Nozzle
1000
Nuclear
Reactor
100
8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year
Power density too high to keep junctions at low temp

Not Only Microprocessors
Cell
Phone
Small Power
Signal RF RF
Digital Cellular Market

(Phones Shipped) Power
Management
1996 1997 1998 1999 2000

Analog
Units 48M 86M 162M 260M 435M Baseband
Digital Baseband
(DSP + MCU)
(data from Texas Instruments)

Challenges in Digital Design
“Microscopic Problems” “Macroscopic Issues”

• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power Dissipation • Predictability
• Clock distribution. • etc.
Everything Looks a Little Different

…and There’s a Lot of Them!

Productivity Trends
Logic Transistor per Chip (M)
10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000
(K) Trans./Staff - Mo.

Tr./Staff Month.
100 1,000
Complexity
100,000 1,000,000
Productivity
10 58%/Yr. compounded 100
10,000 Complexity growth rate 100,000
1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
1995
1981
1983
1985
1987
1989
1991
1993
1997
1999
2001
2003
2005
2007
2009
Source: Sematech
Complexity outpaces design productivity
© Digital Integrated Circuits2nd Courtesy, ITRS Roadmap Inverter

Why Scaling?
 Technology shrinks by 0.7/generation
 With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
 Cost of a function decreases by 2x
 But …
 How to design chips with more and more functions?
 Design engineering population does not double every
two years…
 Hence, a need for more efficient design methods
 Exploit different levels of abstraction

Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S D
n+ n+

Design Metrics
 How to evaluate performance of a

digital circuit (gate, block, …)?
 Cost
 Reliability
 Scalability
 Speed (delay, operating frequency)
 Power dissipation
 Energy to perform a function

Cost of Integrated Circuits
 NRE (non-recurrent engineering) costs

 design time and effort, mask generation
 one-time cost factor
 Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area

NRE Cost is Increasing

Die Cost
Single die
Wafer
Going up to 12” (30cm)
From http://www.amd.com
Cost per Transistor
cost:
¢-per-transistor
1
0.1 Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

Yield
No. of good chips per wafer
Y 100%
Total number of chips per wafer
Wafer cost
Die cost 
Dies per wafer  Die yield
  wafer diameter/2 2   wafer diameter
Dies per wafer  
die area 2  die area

Defects

 defects per unit area  die area 
die yield  1  
  
 is approximately 3
die cost  f (die area) 4

Some Examples (1994)
Chip Metal Line Wafer Def./ Area Dies/ Yield Die
layers width cost cm2 mm2 wafer cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC 4 0.80 $1700 1.3 121 115 28% $53

601
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417

Delay Definitions

Ring Oscillator
T = 2  tp  N

A First-Order RC Network
R
vout
vin C
tp = ln (2) t = 0.69 RC
Important model – matches delay of inverter

Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
1 t T Vsupply t T
Pave   p(t )dt   isupply t dt
T t T t

Energy and Energy-Delay
Power-Delay Product (PDP) =

E = Energy per operation = Pav  tp
Energy-Delay Product (EDP) =

quality metric of gate = E  tp

A First-Order RC Network
Vdd
E0->1 = C LVdd2
R PMOS i
vout supply
A1 NETWORK
vAinN CVLout
CL
NMOS
NETWORK
T T Vdd
E 0 1 =  P  t  dt = V dd  i sup ply t  dt = Vdd  CL dV out = C L  V dd 2

0 0 0
T T Vdd
1 2
E
ca p
= P
cap  t  dt =  V i
out ca p  t  dt =  C V dV
L out out
= --- C  V
dd
2 L
0 0 0

Summary
 Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
 Some interesting challenges ahead
 Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
 Understanding the design metrics that govern
digital design is crucial
 Cost, reliability, speed, power and energy
dissipation

The CMOS Inverter: A First Glance
V DD
V in V out
CL

CMOS Inverter
N Well VDD
VDD PMOS 2l
Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS
NMOS
GND

Two Inverters
Share power and ground
Abut cells
VDD
Connect in Metal

CMOS Inverter
First-Order DC Analysis
V DD V DD
Rp
VOL = 0
VOH = VDD
V out VM = f(Rn, Rp)
V out
Rn
V in 5 V DD V in 5 0

CMOS Inverter: Transient Response
V DD V DD
Rp tpHL = f(R on.CL)

= 0.69 RonCL
V out
V out
CL
CL
Rn
V in 5 0 V in 5 V DD
(a) Low-to-high (b) High-to-low

Voltage Transfer
Characteristic

PMOS Load Lines
IDn
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp
V out
IDp IDn IDn

Vin=0 Vin=0
Vin=1.5 Vin=1.5
V DSp V DSp Vout

VGSp=-1
VGSp=-2.5
Vin = V DD+VGSp Vout = V DD+VDSp
IDn = - IDp

CMOS Inverter Load Characteristics
ID n
Vin = 0 Vin = 2.5
PMOS Vin = 0.5 Vin = 2 NMOS
Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1

Vin = 2 Vin = 0.5
Vin = 2.5 Vin = 0
Vout

CMOS Inverter VTC
Vout
NMOS off
2.5 PMOS res
NMOS s at
PMOS res
2
NMOS sat
1.5
PMOS sat
1
NMOS res
PMOS sat NMOS res
0.5
PMOS off
0.5 1 1.5 2 2.5 Vin

Switching Threshold as a function
of Transistor Ratio
1.8
1.7
1.6
1.5
1.4
V (V)
1.3
M
1.2
1.1
0.9
0.8
0 1
10 10
W /W
p n
Determining VIH and VIL
Vout
V OH
VM
V in
V OL
V IL V IH
A simplified approach

Inverter Gain
0
-2
-4
-6
-8
gain
-10
-12
-14
-16
-18
0 0.5 1 1.5 2 2.5
V (V)
in

Gain as a function of VDD
2.5 0.2
2
0.15
1.5
Vout (V)
Vout(V)
0.1
0.05
0.5
Gain=-1
0
0 0 0.05 0.1 0.15 0.2
0 0.5 1 1.5 2 2.5 V (V)
V (V) in
in

Simulated VTC
2.5
1.5
Vout(V)
0.5
0
0 0.5 1 1.5 2 2.5
V (V)
in

Impact of Process Variations
2.5
2
Good PMOS
Bad NMOS
1.5
Vout(V)
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0 0.5 1 1.5 2 2.5
Vin (V)

Propagation Delay

CMOS Inverter Propagation Delay
Approach 1
VDD
tpHL = CL Vswing/2
Iav
Vout CL
~
Iav CL kn VDD
Vin = V DD

CMOS Inverter Propagation Delay
Approach 2
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
Vout ln(0.5)
CL
1 VDD
Ron
0.5
0.36
Vin = V DD
t
RonCL

CMOS Inverters
VDD
PMOS
1.2mm
=2l
Out
In
Metal1
Polysilicon
NMOS
GND

Transient Response
3
2.5
?
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
Vout(V)
tpLH tpHL
1
0.5
-0.5
0 0.5 1 1.5 2 2.5
t (sec) -10
x 10

Design for Performance
 Keep capacitances small

 Increase transistor sizes
 watch out for self-loading!
 Increase VDD (????)

Delay as a function of VDD
5.5
4.5
4
tp(normalized)
3.5
2.5
1.5
1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
V (V)
DD
Device Sizing
-11
x 10
3.8
3.6 (for fixed load)
3.4
3.2
tp(sec)
2.8 Self-loading effect:

2.6 Intrinsic capacitances
dominate
2.4
2.2
2
2 4 6 8 10 12 14
S

NMOS/PMOS ratio
-11
x 10
5
tpLH tpHL
4.5
tp b = Wp/Wn
tp(sec)
3.5
3
1 1.5 2 2.5 3 3.5 4 4.5 5
b

Impact of Rise Time on Delay
0.35
0.3
tpHL(nsec)
0.25
0.2
0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)

Inverter Sizing

Inverter Chain
In Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.

Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
W
• Analyze as an RC network
1 1
 WP   WN 
RP  Runit    Runit    RN  RW
 Wunit   Wunit 
Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL
W
Load for the next stage: C gin  3 Cunit
Wunit
Inverter with Load
Delay
RW
CL
RW Load (CL)
tp = k RWCL
k is a constant, equal to 0.69

Assumptions: no load -> zero delay
Wunit = 1
Inverter with Load
CP = 2Cunit Delay
2W
W
Cint CL
Load
CN = Cunit
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

Delay Formula
Delay ~ RW Cint  C L 
t p  kRW Cint 1  C L / Cint   t p 0 1  f /  
Cint = Cgin with   1

f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit

Apply to Inverter Chain
In Out
1 2 N CL
tp = tp1 + tp2 + …+ tpN

 C gin, j 1 
t pj ~ RunitCunit 1  
 C 
 gin, j 
N N  C gin, j 1 
t p   t p , j  t p 0  1  , C gin, N 1  C L
 C
i 1 

j 1 gin, j 

Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors

C gin, j  C gin, j 1C gin, j 1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay

Optimum Delay and Number of
Stages
When each stage is sized by f and has same eff. fanout f:
f N  F  CL / Cgin,1
Effective fanout of each stage:
f NF
Minimum path delay

t p  Nt p 0 1  N F /  
Example
In Out
1 f f2 CL= 8 C1
C1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2

Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
CL  F  Cin  f Cin with N 
N
ln f
t p 0 ln F  f  

t p  Nt p 0 F /   1 1/ N
  
  ln f ln f


t p t p 0 ln F ln f  1   f
  0
f  ln f 2
For  = 0, f = e, N = lnF f  exp 1   f 

Optimum Effective Fanout f
Optimum f for given process defined by 
f  exp 1   f 
fopt = 3.6
for =1

Impact of Self-Loading on tp
No Self-Loading, =0 With Self-Loading =1
60.0
40.0
u/ln(u)
x=10,000
x=1000
20.0 x=100
x=10
0.0
1.0 3.0 5.0 7.0
u

Normalized delay function of F

t p  Nt p 0 1  N F /  

Buffer Design
N f tp
1 64 1 64 65
1 8 64
2 8 18
1 4 16 64 3 4 15
1 64 4 2.8 15.3
2.8 8 22.6

Power Dissipation

Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors

Dynamic Power Dissipation
Vdd
Vin Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.

Modification for Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E 0  1 = CL  Vdd   Vdd – Vt 
Can exploit reduced sw ing to low er power

(e.g., reduced bit-line swing in memory)

Adiabatic Charging
2 2

Adiabatic Charging

Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E N = CL  V dd2  n N 
EN : the energy consumed for N clock cycles

n(N ): the number of 0->1 transition in N clock cycles
EN n N  2
P = lim --------  f =  lim ------------  C V  f clk
avg N   N clk N   N  L dd
n N 
0  1 = lim ------------
N N
P avg = 0 1  C  Vdd 2  f clk

 L

Transistor Sizing for Minimum
Energy In Out
Cext
Cg1 1 f
 Goal: Minimize Energy of whole circuit

 Design parameters: f and VDD
 tp  tpref of circuit with f=1 and VDD =Vref
 f  F 
t p  t p 0  1    1   
    f  
VDD
t p0 
VDD  VTE

Transistor Sizing (2)
 Performance Constraint (=1)
 F  F
 2  f    2  f  
tp t p0  f  VDD Vref  VTE  f 
  1
t pref t p 0 ref 3  F  Vref VDD  VTE 3  F 
 Energy for single Transition
E  VDD
2
C g1 1   1  f   F 
2
E  VDD   2  2 f  F 
   
 
Eref  Vref   4  F 

Transistor Sizing (3)
VDD=f(f) E/Eref=f(f)
4 1.5
3.5
F=1
3
normalized energy
2 1
2.5
vdd (V)
2 5
1.5
0.5
1
10
0.5 20
0 0
1 2 3 4 5 6 7 1 2 3 4 5 6 7
f f

Short Circuit Currents
Vd d
Vin Vout
CL
0.15
0.10
IVDD (mA)
0.05
0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,

but can’t do this for cascade logic, so ...
Minimizing Short-Circuit Power
8
Pnorm
5
Vdd =3.3
4
Vdd =2.5
3
1
Vdd =1.5
0
0 1 2 3 4 5
t /t
sin sout

Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues

Sub-Threshold
in low-energy circuitCurrent
design!Dominant Factor

Reverse-Biased Diode Leakage
GATE
p+ p+
N
Reverse Leakage Current

+
V
- dd
IDL = JS  A
2
JS = JS
1-5pA/ mmpA/mm2
= 10-100 for a 1.2 mm
at 25 degCMOS technology
C for 0.25mm CMOS
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature

Subthreshold Leakage Component

Static Power Consumption
Vd d
Istat
Vout
CL
Vin =5V
Pstat = P(In=1).Vdd . Istat
Wasted •energy … over dynamic consumption

Dominates
Should be avoided in almost all cases,
• Not a function of switching frequency
but could help reducing energy in others (e.g. sense amps)

Principles for Power Reduction
 Prime choice: Reduce voltage!
 Recent years have seen an acceleration in
supply voltage reduction
 Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
 Reduce switching activity
 Reduce physical capacitance
 Device Sizing: for F=20
– fopt(energy)=3.53, fopt(performance)=4.47

Impact of
Technology
Scaling

Goals of Technology Scaling
 Make things cheaper:

 Want to sell more functions (transistors)
per chip for the same money
 Build same products cheaper, sell the
same part for less money
 Price of a transistor has to be reduced
 But also want to be faster, smaller,
lower power

Technology Scaling
 Goals of scaling the dimensions by 30%:

 Reduce gate delay by 30% (increase operating
frequency by 43%)
 Double transistor density
 Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
 Die size used to increase by 14% per
generation
 Technology generation spans 2-3 years

Technology Generations

Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors

Year of
1999 2000 2001 2004 2008 2011 2014
Introduction
Technology node
180 130 90 60 40 30
[nm]
Supply [V] 1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6
Wiring levels 6-7 6-7 7 8 9 9-10 10
Max frequency 14.9
1.2 1.6-1.4 2.1-1.6 3.5-2 7.1-2.5 11-3
[GHz],Local-Global -3.6
Max mP power [W] 90 106 130 160 171 177 186
Bat. power [W] 1.4 1.7 2.0 2.4 2.1 2.3 2.5
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

Technology Evolution (1999)

ITRS Technology Roadmap
Acceleration Continues

Technology Scaling (1)
2
10
Minimum Feature Size (micron)
1
10
0
10
-1
10
-2
10
1960 1970 1980 1990 2000 2010
Year
Minimum Feature Size

Number of components per chip

tp decreases by 13%/year
50% every 5 years!
Propagation Delay

rs

ea
100 x1.4 / 3 y 1000
0.7
Power Dissipation (W)
Power Density (mW/mm2 )

ears

y
3
10 / 3
x4

100
10
0.1
MPU
DSP
0.01 1
1 10
80 85 90 95 Scaling Factor 
Year （normalized by 4 mm design rule ）
(a) Power dissipation vs. year. (b) Power density vs. scaling factor.
From Kuroda
Technology Scaling Models
• Full Scaling (Constant Electrical Field)

ideal model — dimensions and voltage scale
together by the same factor S
• Fixed Voltage Scaling

most common model until recently —
only dimensions scale, voltages remain constant
• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors

Scaling Relationships for Long Channel Devices

Transistor Scaling
(velocity-saturated devices)

mProcessor Scaling
P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001

mProcessor Power

mProcessor Performance

2010 Outlook
 Performance 2X/16 months
 1 TIP (terra instructions/s)
 30 GHz clock
 Size
 No of transistors: 2 Billion
 Die: 40*40 mm
 Power
 10kW!!
 Leakage: 1/3 active Power

Some interesting questions
 What will cause this model to break?

 When will it break?
 Will the model gradually slow down?
 Power and power density
 Leakage
 Process Variation

Moore's Law: Electronics, April 19, 1965

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LOG2 OF THE NUMBER OF

COMPONENTS PER INTEGRATED FUNCTION

© Digital Integrated Circuits2nd

Electronics, April 19, 1965.

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Courtesy, Intel Inverter

100 2X growth in 1.96 years!

© Digital Integrated Circuits2nd Courtesy, Intel Inverter

Die size grows by 14% to satisfy Moore’s Law

© Digital Integrated Circuits2nd Courtesy, Intel Inverter

© Digital Integrated Circuits2nd Courtesy, Intel Inverter

Lead Microprocessors power continues to increase

© Digital Integrated Circuits2nd Courtesy, Intel Inverter

Power delivery and dissipation will be prohibitive

© Digital Integrated Circuits2nd Courtesy, Intel Inverter

Power density too high to keep junctions at low temp

© Digital Integrated Circuits2nd Courtesy, Intel Inverter

Digital Cellular Market

1996 1997 1998 1999 2000

(data from Texas Instruments)

© Digital Integrated Circuits2nd Inverter

“Microscopic Problems” “Macroscopic Issues”

Everything Looks a Little Different

© Digital Integrated Circuits2nd Inverter

(K) Trans./Staff - Mo.

Complexity outpaces design productivity

© Digital Integrated Circuits2nd Courtesy, ITRS Roadmap Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

 How to evaluate performance of a

© Digital Integrated Circuits2nd Inverter

 NRE (non-recurrent engineering) costs

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

Going up to 12” (30cm)

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

die cost  f (die area) 4

© Digital Integrated Circuits2nd Inverter

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 4 0.80 $1700 1.3 121 115 28% $53

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

Important model – matches delay of inverter

© Digital Integrated Circuits2nd Inverter

Power-Delay Product (PDP) =

Energy-Delay Product (EDP) =

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

Rp tpHL = f(R on.CL)

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

IDp IDn IDn

V DSp V DSp Vout