Overview

• MIPI CSI-2 is a sensor interface commonly used

in embedded systems to connect an image
sensor to an embedded board that controls it
and processes the image data. The board and the
sensor together act as a camera.
• We implemented MIPI CSI-2 as a camera
interface, creating a complete camera module
with advanced image pre-processing capabilities
that can be connected to an embedded board.
Features
• Supports up to 4-Data lanes.
• Each Data lane supports up to 1.5Gbps.
• Supports pixel interface on the application side and
only the primary data format is supported.
• Supports Camera control Interface for controlling
the CSI2 Transmitter.
• Supports ECC -single bit Error correction and
double bit error detection for packet headers.
• Supports CRC error checking.
• Supports High speed data, Ultra Low power (Escape
mode) control and low power data modes
MIPI-Physical Layers
• The physical layer, or PHY, is the heart of any
interconnection solution.
• MIPI Alliance offers a family of three high-
performance and cost-optimized physical layers:
MIPI D-PHY, MIPI M-PHY and MIPI C-PHY.
• MIPI D-PHY is used primarily to interconnect
cameras and displays to an application
processor.
MIPI D-PHY
• MIPI D-PHY is a physical serial data
communication layer on which the protocols like
CSI (Camera Serial Interface), DSI (Display
Serial Interface) runs.
• D-PHY is a high speed, low power, source
synchronous physical layer.
• Supports High Speed (HS) Mode and Low power
mode(Escape) of operation.
• It has a peculiar ability of sending the high speed
and low power data in the single packet burst.
Camera Serial Interface
• The Camera Serial Interface (CSI) is a
specification of the Mobile Industry Processor
Interface (MIPI) Alliance.
• It defines an interface between a camera and a
host processor.
• CSI-2 uses the MIPI D-PHY specification for the
data transport PHY and CSI-2’s Camera Control
Interface (CCI), compatible with I2C, as the
control channel.
Camera Serial Interface Implementation
CSI2 Receiver Module
• The CSI2RX module consists of following sub-
blocks
▫ Lane Management
▫ Low-Level Protocol
▫ Byte to Pixel Conversion
▫ Camera Control Interface
▫ APB Slave Interface for Register access
Lane Management Module
• The lane management module interfaces with D-
PHY(One per lane) on one side and Low Level
Protocol module on other side.
▫ Supports 4-DPHY Interfaces, one for each lane.
▫ The number of lanes supported has to be configured
during the generation of IP.
▫ Supports High Speed (HS) Mode and Low power
mode(Escape) of operation.
▫ It implements 4-Async FIFO with each of size 16-deep
and 10-bit wide to convert the data from the DPHY
clock domain(1.5 Gbps per lane) to the User clock
domain(250-MHz).
Low Level protocol module
• LLP module receives 32-bit data from the Lane
management module and checks for ECC/CRC
errors and provides the same 32-bit data to the
Byte2Pixel module.
• This module receives short and long packet from
the Lane management module.
• Short packet will have only 32-bit packet
headers and no payload.
• Long packet will have 32-bit Packet Header,
Payload and 16-bit CRC(Packet Footer).