Simple As Possible- 2

Microprocessor
Design
 SAP-2 Registers

Subroutine Counter (SC)

The subroutine counter can pitch bits for the program counter during two
components run. This occurs when a new instruction takes program control
away from the PC at given it to the SC.

Program Counter (PC)

It has 8-bits therefore it can count from 00H to FFH and has 256 memory
locations. A CLR signal resets the PC before each computer run.

Memory Address Register (MAR)

It receives 8 bit address from the PC/SC which ever has program control
during fetch cycle also it receives an 8-bits address field from the IR during
an execution cycle.
 SAP-2 Registers

Random Access Memory (RAM)

The 256X12 RAM can store many 256 words at 12 bits, which mean that
it has addressable memories with a 12-bit word length. With WE low and
ME high, the content of the address is read into the W-Bus. With WE and
ME high, the contents of the MDR are written into the addressed RAM.
Memory Data Register(MDR)
MDR has 3-state output; therefore a high Ed reads the content of the MDR
into the W-bus. The 2-state output is connected to the RAM so that during
a high LD and positive CLK edge the 2-state output then set the RAM.
 SAP-2 Registers

Instruction Register (IR)

During the execution of a memory-reference or jump instruction, the 4
MSBs in the IR represent the instruction field and 8 LSBs are the address
field.
During the execution of an operate instruction, the 8 MSBs in the IR form
the instruction field and the 4 LSBs are don’t cares.
Control Unit (CU)
Control word contains 28 bits and it provides CLR, CLK and other control
pins. It coordinates and synchronizes all registers. Although a control
word is bigger, the idea is the same, the con bit determine how the register
react to the next positive CLK edge.
 SAP-2 Registers
Input Register (I)

Interface circuits convert signals from peripheral devices to binary signals suitable for entry
into a computer. A high LN load this word into the Input register and a high EN can read
the input word onto the W bus for transfer to the accumulator.

Accumulator

The two-state output goes directly to the arithmetic logic unit ALU. The three-state output
goes to the W bus. Therefore, the 12-bit accumulator word continuously drives the ALU;
the same word appears on the W bus when EA is high.

Arithmetic Logic Unit (ALU)

It has 4 select bits that determine the arithmetic and logic operation performed on words A
and B.
The select bits S3 through S0 cover 0000 through 1111, which can select 16 arithmetic and
logic functions. SAP-2 uses three arithmetic functions (NULL, ADD, SUB) and seven logic
functions (Complement A, Complement B, OR, AND, NOR, NAND, and XOR).
 SAP-2 Registers

B Register
The high LB and positive clock edge load the word on the W bus into the
B register. The two- state output of the B register drives the ALU.
Index Register (X)
The index register has an increment input INX and a decrement input
DEX.
High INX means index register counts up; High DEX means it counts
down.
Output Register (O)
The output register connects to an interface circuit. The interface
circuit converts the contents of the output register into signals suitable
for driving the peripheral devices
SAP-2 Instruction Set
Memory Reference Instructions

 All SAP-2 instructions use the memory during the

fetch cycle because a program instruction is
transferred from the memory to the instruction
register.
 During the execution cycle, however, the memory
may or may not be used; it depends on the type of
instruction that has been fetched.
 LDA, ADD and SUB

 LDA means “load to the accumulator”

 ADD means “add to the accumulator”
 SUB means “subtract from the accumulator”
 Any word being loaded, added, subtracted, or
otherwise operated on is called is called an operand.
 For instance, LDA 23 means “load the accumulator
with R23”, R23 is an operand while 23 is the address
of the operand.
 STA

 Mnemonic for “store the accumulator word.”

 Every STA instruction includes a
memory address.
 For example, STA 56 means “store the
accumulator word at address 56.”
 LDB and LDX

 LDB is the mnemonic for “load the B

register,” and LDX is the mnemonic for
“load the index register.”
 These instructions must include an
address.
 For instance, LDB 45 means “load the B
register with R45
 Jump Instructions

 SAP-2 has six jump instructions; these

can change the program sequence.
Instead of fetching Instructions at
successive addresses, the computer may repeat or
skip part of the program after a jump instruction has
been executed.
 JMP

 Mnemonic for “jump the program counter”

 Every JMP instruction includes an address to be
loaded into the PC rather than the MAR.
 When a JMP instruction is in the IR, the CON
sends out high EI and LP. The T3 phase of any
JMP instruction, therefore results in PC=address.
 The T4 and T5 are donothings.
 LP
PC
CLK

8-bit address
CLK
Field
IR
EI

CON

High EI and LP

T3 Phase of JMP Instruction

R40 = ADD 80 R48 = LDX 95
R41 = SUB 81 R49 = ADD 96
. R50 = JMP 70
. R51 = ADD 97
. R52 = STA 98
R50 = STA 91 .
R51 = SUB 92 .
R52 = LDX 93 .
R53 = JMP 40 R70 = LDX 83
 JAM

 Mnemonic for “jump the program counter if the

accumulator is minus.
 Every JAM instruction includes the address to be loaded
into the PC.
 For instance, JAM 40 means “jump to address 40 if
accumulator is minus.”
 JAZ

 Mnemonic for “jump the program counter if the

accumulator is zero.”
 Every JAZ instruction includes the address to be loaded into
the PC.
 JIM AND JIZ

 JIM is the mnemonic for “jump the program

counter if the index register is minus.” while
JIZ is the mnemonic for “jump the program
counter if the index register is zero.”
 Every JIM and JIZ instruction includes
the address to be loaded into the PC.
 JAM, JAZ, JIM and JIZ are called
conditional jumps because the
program jump occurs only if certain
conditions are satisfied. JMP is
unconditional; once this instruction is
fetched, the execution cycle always
jumps the program to the specified
address.
 JMS

 Mnemonic for “jump to subroutine”.

 Every JMS instruction must include the starting address of the
desired subroutine.
 When a JMS is executed, program control passes from the
program counter to the subroutine counter. After each
subroutine

instruction is fetched, the SC is

incremented by one.
 JMS is unconditional like JMP.
 OPERATE INSTRUCTIONS

 An operate instructions neither uses the

memory nor alters the program counter.
Instead, it operates on words already
transferred out of memory into working
registers.
 These are NOP, CLA, XCH, DEX, INX, CMA,
CMB, IOR, AND, NOR, NAN, XOR, BRB,
INP, OUT, HLT
 NOP
 NOP mnemonic for “no operation.
 During the execution of a NOP
instructions, all the phases are do
nothings. Therefore, nothing happens
when a NOP is executed.

CLA
 CLA means “clear the accumulator”.
 The execution of a CLA resets all
accumulator bits to zero.
 XCH
 XCH is the mnemonic for “exchange
accumulator and index.”
 During the execution of an XCH, the words
in the accumulator and index register are
interchanged.

DEX
 DEX means “decrement the index
register.”
 The execution of a DEX decreases the
contents of the index register by one.
 INX
 INX means “increment the index register.”
 This instruction adds one to the index
register.

CMA
 CMA stands for “complement the
accumulator.”
 The execution of a CMA inverts each bit in
the accumulator, producing 1’s
complement.
 CMB
 CMB stands for “complement the B
register.”
 This instruction inverts each bit in the B
register, resulting in the 1’s complement.

IOR
 IOR means “inclusive OR,” identical to the
OR function. The execution of an IOR will
OR the corresponding bits in the
accumulator and B register, the result
appears in the accumulator.
 AND, NOR, NAN, XOR perform bitwise
operation to the content of the
accumulator and B register.
BRB
 BRB is the mnemonic for “branch back”.
The BRB is used at the end of each
subroutine to get back to the main
program. BRB is to a subroutine as HLT is
to the main program.
 INP
 INP means “input”. This instruction is
executed in two phases. The first
execution phase loads the input register
with a word from the interface circuit. The
second execution phase transfers this
word to the accumulator.

OUT
 OUT stands for “output”. When the
instruction is executed, the accumulator
word is loaded into the output register.
 Op-code and Select Code
1111 XXXX XXXX
Op code
Select code
Don’t cares
To program any operate instruction, start with four 1s, follow the
select code , and end with four don’t cares.
NOP = 1111 0000 XXXX
CLA = 1111 0001 XXXX
MRIs and jump instructions use an address field but operate
instructions don’t, because all the operands are already in the
working registers.
 SAP-2 Programming

 Create a
program a
program that
multiplies two
integers. Use 12
and 8 for this
example.
 SAP-2 Programming

 Input a number from

interface circuit to
determine if it’s odd.
If the number is odd,
the computer is to
answer YES by
loading 1111 1111
1111 into the output
register. If the
number is even, the
computer is to
answer NO by loading
0000 0000 0000 into
the output register.
JMP Circuit and JMS Flag
JMP Circuit and JMS Flag
Instruction Register