Interfacing with ICs

Dr.C.Sheeba Joice
Professor & Deputy Head/ECE
Saveetha Engineering College
Chennai – 602 105
CONTENTS
• Introduction – Interfacing
• 8255 – Programmable Peripheral Interface
• 8259 – Programmable Interrupt Controller
• 8254 – Programmable Counter/Interval
Timer
• 8237 – Programmable DMA Controller
Introduction
8255 - Programmable
Peripheral Interface (PPI)
Block
Diagram
of 8255
PIN CONFIGURATION OF 8255
Selection of 8255 ports using address lines.
Programming the 8255
• Three basic modes of operation
– Mode 0 (Basic I/O): three simple I/O ports.
• Ports A and B operate as either inputs or outputs.
• Port C is divided into two 4-bit groups either of which
can be operated as inputs or outputs.
– Mode 1 (Strobed I/O): two hand shaking I/O
ports.
• Ports A and B operate as either inputs or outputs as in
mode 0
• Port C is used for handshaking and control.
– Mode 2 (Strobed Bidirectional I/O): a
bidirectional I/O port with five hand shaking
signals.
• Port A is bidirectional (both input and output).
• Port C is used for handshaking.
• Port B is not used.
 Control
Word
Format of
8255
Programming the 8255
• Write the 80x86 initialization routine
required to program the 8255,for mode 0,
with port A as an output and ports B and C
inputs
– The control word is formed as:
• 1 00 0 1 0 1 1 = 8BH
– The program is as follows:
• MOV AL,8BH ;Control byte to AL
• OUT 6,AL ;Write to control port
Programming the 8255
• Write an 80x86 program to input a byte
from port B of the PPI chip in pervious
example and output this byte to port A of
the same chip. Assume the chip has been
programmed as in the previous example.

– The program requires two instructions.

• IN AL, 2 ; Get data from port B
• OUT 0,AL ; Output the data to port A
Mode 1 input.
Mode 1 output
Mode 2 control signals.
8259 – Programmable Interrupt Controller
Interrupt
• An interrupt is an event which informs the
CPU that its service (action) is needed.
• Interrupt Procedure
• Types – MI, NMI
• Pins – INTR, INTA
• Sources of interrupts:
– Internal fault (e.g.. divide by zero, overflow)
– Software
– External hardware
– Reset
8259 - Programmable Interrupt
Controller (PIC)
• Tool for managing interrupt requests.
• 8259 is a very flexible peripheral controller
chip:
– PIC can deal with up to 64 interrupt inputs
– interrupts can be masked
– various priority schemes can also
programmed.
Block Diagram of 8259
Pin diagram of 8259
FUNCTIONS OF 8259
• Manage 8 Interrupts
• Any Memory location is possible
• Resolve 8 levels of Interrupt Priorities
• Mask each interrupt individually
• Read status of Pending, In-service& Masked
interrupts
• Accept either Level triggered or edge triggered
interrupt request
• Expanded to 64 priority levels by cascading
 INTA INT

D0-D7 Control Logic

Data Bus
Buffer

Bus
RD Read/
WR Write IR0
Interrupt
A0 Logic IN Priority Request IR1
Service Resolver Register
CS Register IRR
ISR
CAS0 IR7
Cascade
CAS1 Buffer/
CAS2 Comparator
Interrupt Mask Register
SP / EN IMR

Internal Bus
INTERRUPT OPERATION

• EI
• Control Words in the Control Register – To initialize
8259
• 2 Types of Control Words:
1. Initialization Command Words (ICWs)
2. Operational command Words (OCWs)
INTERRUPT OPERATION
• IRR stores the requests
• PR examines IRR,IMR,ISR
• INTA from MPU
• Appropriate bit in ISR is SET & corresponding bit in IRR
is RESET
• Opcode for CALL placed in data bus
• Decodes CALL & sends 2 INTA signals
• CALL address – Vector memory location – placed in
Control register during initialization
• ISR bit RESET – (1) AEOI (2) EOI (by ICW)
 Operating Modes of 8259

Priority Modes

• Fully Nested Mode :

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
4 5 6 7 0 1 2 3

• Automatic Rotation Mode:

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
5 6 7 0 1 2 3 4

• Specific Rotation Mode:

END OF INTERRUPT

• Non Specific EOI Command

• Specific EOI Command

• Automatic EOI
Additional Features

• Interrupt Triggering

• Interrupt Status

• Poll Method
Programming 8259A
Initialization Command Words ICW1 and ICW2

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 A7 A6 A5 1 LTIM ADI SNGL IC4

A7-A5 of Interrupt ICW1

1 = ICW4 Needed
vector address MCs
0 = No ICW4 Needed
80/85 mode only
1 – Single
1 – Level Triggered 0 - Cascaded
0 – Edge Triggered
Call Address Interval
1 – Interval of 4 bytes
ICW2 0 – Interval of 8 bytes.
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 A15 A14 A13 A12 A11 A10 A9 A8

• A15 – A8 of interrupt vector address

• A0 =1 selects ICW2
 Operation Command Words

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0

1 – Mask Set
0 – Mask Reset
OCW1

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 RSM SSM 0 1 P RR RIS

OCW3
1 – Poll 0 0 No Action
No Action 0 0 Command 0 1
0 1 0 – No Poll Read IRR on next
Reset Special 1 0
1 0 Command RD pulse
Mask 1 1
Set Special 1 1 Read IRR on next
Mask RD pulse
 Operation Command Word
OCW2
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 R SL EOI 0 0 L2 L1 L0

0 1 2 3 4 5 6 7
0 1 0 0 0 1 0 1
0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1

END OF
INTERRUPT 0 0 1 NON-SPECIFIC EOI COMMAND
0 1 1 SPECIFIC EOI COMMAND
1 0 1 ROTATE ON NON-SPECIFIC EOI MODE (SET)
AUTOMATIC
1 0 0 ROTATE IN AUTOMATIC EOI MODE (SET)
ROTATION 0 0 0 ROTATE IN AUTOMATIC EOI (CLEAR)
SPECIFIC 1 1 1 ROTATE ON SPECIFIC EOI COMMAND
ROTATION 1 1 0 SET PRIORITY COMMAND*
0 1 0 NO OPERATION
* - In this Mode L0 – L2 are used
Two cascaded PICs
 8253
Programmable Interval
Timer/Counter
Applications
• Real time clock
• Event Counter
• Digital One shot
• Square wave generator
• Complex wave form generator
Pin Configuration
Block Diagram
Internal 8254 Registers
RD WR A0 A1 Function

1 0 0 0 Load counter 0
COUNTER 0
0 1 0 0 Read counter 0

1 0 0 1 Load counter 1
COUNTER 1
0 1 0 1 Read counter 1

1 0 1 0 Load counter 2
COUNTER 2
0 1 1 0 Read counter 2

MODE WORD or
1 0 1 1 Write mode word
CONTROL WORD

-- 0 1 1 1 No-operation
 Control Word Format
D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

SC – Select Counter

SC1 SC0

0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Illegal
RL – Read/Load
RL1 RL0
0 0 Counter Latching operation
1 0 Read / Load most significant byte only
0 1 Read / Load least significant byte only
1 1 Read / Load least significant byte first, then MSB

Mode Selection: BCD:

M2 M1 M0 MODE 0 Binary Counter 16 bits
0 0 0 Mode 0 1 Binary Coded Decimal (BCD)
0 0 1 Mode1 Counter (4 decade)
X 1 0 Mode2
X 1 1 Mode3
1 0 0 Mode4
1 0 1 Mode5
 Programming the 8254
Write Operations :
• To initialize the counter
1. Write control word
2. Load LSB of a count in the counter Reg.
3. Load MSB of a count in the counter Reg.

Read Operations:
• Inhibition
• Reading on the fly
Gate Settings of a Counter
Signal
Status Low or going low Rising High
Mode
Enables
0 Disables counting --
counting
1
1) Initiates counting
-- --
2) Resets output after next clock

1) Disables counting
2 1) Reloads counter Enables
2) Sets output
2) Initiates counting counting
immediately high
1) Disables counting
Enables
3 2) Sets output Initiates counting
counting
immediately high
Enables
4 Disables counting --
counting
5 -- Initiates counting --
Mode Description
D3 D2 D1
Mode value
M2 M1 M0

0 0 0 mode 0: interrupt on terminal count

0 0 1 mode 1: programmable one-shot

x 1 0 mode 2: rate generator

x 1 1 mode 3: square wave generator

1 0 0 mode 4: software triggered strobe

1 0 1 mode 5: hardware triggered strobe

MODE 0
Interrupt on Terminal Count
MODE 1
Programmable One - Shot
MODE 2
Rate Generator Clock
MODE 3
Square Wave Generator
MODE 4
Software Triggered Strobe
MODE 5
Hardware Triggered Strobe
8274 – Programmable
DIRECT MEMORY ACCESS
Controller
Direct Memory Access
– An important aspect governing the Computer System
performance is the transfer of data between memory
and I/O devices.

– The operation involves loading programs or data files

from disk into memory, saving file on disk, and
accessing virtual memory pages on any secondary
storage medium.
Computer System with DMA
Implementing DMA in a
Computer System
• A DMA controller implements direct memory
access in a computer system.
• It connects directly to the I/O device at one end
and to the system buses at the other end. It also
interacts with the CPU, both via the system
buses and two new direct connections.
• It is sometimes referred to as a channel. In an
alternate configuration, the DMA controller may
be incorporated directly into the I/O device.
Data Transfer using DMA
Controller
• To transfer data from an I/O device to memory,
the DMA controller first sends a Bus Request to
the CPU by setting BR to 1. When it is ready to
grant this request, the CPU sets it’s Bus grant
signal, BG to 1.
• The CPU also tri-states it’s address,data, and
control lines thus truly granting control of the
system buses to the DMA controller.
• The CPU will continue to tri-state it’s outputs as
long as BR is asserted.
DMA Registers
• Address Register
• Memory address to be used in the data transfer.
• The CPU treats this signal as one or more output ports.
• Count Register, also called (Word Count Register)
• Contains the no. of bytes of data to be transferred.
• Treated as an O/P port (with a diff. Address) by the CPU.
• Control Register
• Accepts commands from the CPU.
• Treated as an O/P port by the CPU.
• Status Register
• Supplies information to the CPU,
• Treated as an I/P port
Internal Configuration of
DMA Controller
DMA Transfer Modes
Modes vary - DMA controller determines when to
transfer data.

• BURST mode
– Sometimes called Block Transfer Mode.
– An entire block of data is transferred in one contiguous
sequence. Once the DMA controller is granted access to the
system buses by the CPU, it transfers all bytes of data in the
data block before releasing control of the system buses back to
the CPU.
– This mode is useful for loading programs or data files into
memory, but it does render the CPU inactive for relatively long
periods of time.
CYCLE STEALING Mode

– Viable alternative for systems in which the CPU

should not be disabled for the length of time needed
for Burst transfer modes.
– DMA controller obtains access to the system buses
as in burst mode, using BR & BG signals.
– However, it transfers one byte of data and then
deasserts BR, returning control of the system buses
to the CPU. It continually issues requests via BR,
transferring one byte of data per request, until it has
transferred it’s entire block of data.
– By continually obtaining and releasing control of the
system buses, the DMA controller essentially
interleaves instruction & data transfers. The CPU
processes an instruction, then the DMA controller
transfers a data value, and so on.
– The data block is not transferred as quickly as in
burst mode, but the CPU is not idled for as long as
in that mode.
– Useful for controllers monitoring data in real time.
TRANSPARENT Mode

– This requires the most time to transfer a block of data,

yet it is also the most efficient in terms of overall
system performance.
– The DMA controller only transfers data when the CPU
is performing operations that do not use the system
buses.
– For example, the Relatively simple CPU has several
states that move or process data solely within the
CPU:
NOP1: (No operation)
LDA C5: ACDR
 JUMP 3: PCDR,TR
CLAC 1: AC0, Z1
– Primary advantage is that CPU never stops executing
its programs and DMA transfer is free in terms of time.
– Disadvantage is that the hardware needed to
determine when the CPU is not using the system
buses can be quite complex and relatively expensive.
Modification of the CPU to
work with DMA
• Addition of control input BR and control output
BG, along with the logic to generate BG.
• The logic depends on when the designer wants
the CPU to be able to grant control of the system
buses to the DMA controller.
• Most CPUs allow DMA requests to be granted
after the instruction has been fetched; after it
has been decoded, after it’s operations have
been fetched ; after the instruction has been
executed, and after it’s results have been stored.
Summary

• Advantages of DMA
– Computer system performance is improved by direct
transfer of data between memory and I/O devices,
bypassing the CPU.
– CPU is free to perform operations that do not use
system buses.

• Disadvantages of DMA
– In case of Burst Mode data transfer, the CPU is
rendered inactive for relatively long periods of time.
Thank You