Chapter 4

Combinational Logic

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 1

 Outline
4.1. Combinational Circuits
4.2. Analysis Procedure
4.3. Design Procedure
4.4. Binary Adder-Subtractor
4.5. Decimal Adder
4.6. Binary Multiplier
4.7 Magnitude Comparator
4.8. Decoders
4.9. Encoders
4.10.Multiplexers

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 2

 4.1. Combinational Circuits

A combinational circuit consists of logic gates whose

outputs at any time are determined from only the
present combination of inputs.

The diagram of a combinational circuit has logic gates with

no feedback paths or memory elements .

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 3

 4-2. Analysis procedure
 For Analysis of combinational circuits:

 Verify that is circuit is combinational.

 Boolean functions using truth table or logic diagrams

 To obtain the output Boolean functions from a logic

diagram, proceed as follows:

1. Label all gate outputs that are a function of input variables

with arbitrary symbols. Determine the Boolean functions
for each gate output.

2. Label the gates that are a function of input variables and

previously labeled gates with other arbitrary symbols. Find
the Boolean functions for these gates.
CEN - 220 4
 4-2. Analysis procedure

3. Repeat the process outlined in step 2 until the outputs of

the circuit are obtained.

4. By repeated substitution of previously defined functions,

obtain the output Boolean functions in terms of input
variables.

CEN - 220 5
 Example
F2 = AB + AC + BC; T1 = A + B + C; T2 = ABC; T3 = F2’T1;
F1 = T3 + T2
F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC

CEN - 220 6
 Derive truth table from logic
diagram
 We can derive the truth table in Table 4-1 by using
the circuit of Fig.4-2.

CEN - 220 7
 Circuit implementation
z = D’; y = CD + C’D’ = CD + (C + D)’
x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’
w = A + BC + BD = A + B(C + D)

CEN - 220 8
 4-4. Binary Adder-Subtractor
 A combinational circuit that performs the addition of two bits
is called a half adder.
 The truth table for the half adder is listed below:

S: Sum
C: Carry

S = x’y + xy’
C = xy

CEN - 220 9
 4.4. Binary Adder-Subtractor

 Half Adder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 10

 Binary Adder-Subtractor

 Full Adder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 11

 Binary Adder-Subtractor

 Full Adder

Simplify!

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 12

 Binary Adder-Subtractor

 Full Adder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 13

 Binary Adder-Subtractor

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 14

 Binary Adder-Subtractor

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 15

 Binary Adder-Subtractor

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 16

 Binary Adder-Subtractor

 Binary Adder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 17

 Binary Adder-Subtractor

 Binary Adder

Ripple Carry Adder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 18

 Binary Adder-Subtractor
 Carry Propagation

Gi is called a carry generate

Pi is called a carry propagate

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 19

 Binary Adder-Subtractor

 Carry Propagation

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 20

 Binary Adder-Subtractor
Carry Propagation

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 21

 Binary Adder-Subtractor

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 22

 Binary Subtractor

Make a binary Subtractor

5 Minutes for the Task!

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 23

 Binary Subtractor

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 24

 OverFlow
When two numbers with n digits each are added and the sum is a
number occupying n + 1 digits, we say that an overflow occurred.

In digital computers because the number of bits that hold the number
is finite and a result that contains n + 1 bits cannot be accommodated
by an n -bit word.

When two unsigned numbers are added, an overflow is detected from

the end carry out of the most significant position
Signed Numbers

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 25

 OverFlow

Signed Numbers

0 1 1 0

1 1

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 26

 4.5. Decimal Adder
Add 0110
 BCD Adder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 27

 4.5. Decimal Adder

BCD Adder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 28

 4.6. Binary Multiplier

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 29

 4.6. Binary Multiplier

J Multiplier bits
K Multiplicand bits

J x K AND gates
(J-1) K-bit adders

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 30

 Binary Multiplier

B3B2B1B0 Multiplicand bits (K)

A2A1A0 Multiplier bits (J)

J x K AND gates
(J-1) K-bit adders

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 31

 4.7 Magnitude Comparator

 A magnitude comparator is a
combinational circuit that compares two
numbers A and B and determines their
relative magnitudes.
 The outcome of the comparison is specified
by three binary variables that indicate whether
A > B, A = B, or A < B.

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 32

 4.7 Magnitude Comparator

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 33

 4.8. Decoders

 A binary code of n bits is capable of

representing up to 2n distinct elements of
coded information.
 A decoder is a combinational circuit that
converts binary information from n input
lines to a maximum of 2n unique output
lines.
 If the n-bit coded information has unused
combinations, the decoder may have fewer
than 2n outputs.
CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 34
 4.8. Decoders

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 35

 4.8. Decoders

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 36

 4.8. Decoders

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 37

 Decoders

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 38

 Combinational Logic Implementation

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 39

 Combinational Logic Implementation

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 40

 4.9. Encoders

 Performs an inverse function of a decoder.

 Encoder has 2n input lines
 Has n output lines

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 41

 4.9. Encoders

 Performs an inverse function of an

decoder.
 Encoder has 2n input lines
 Has n output lines

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 42

 Priority Encoder
 A priority encoder is an encoder circuit that
includes the priority function.
 The operation of the priority encoder is such that
if two or more inputs are equal to 1 at the same
time, the input having the highest priority will take
precedence
 The circuit has a third output designated by V ;
this is a valid bit indicator that is set to 1 when
one or more inputs are equal to 1.
 If all inputs are 0, there is no valid input and V is
equal to 0.

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 43

 Priority Encoder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 44

 Priority Encoder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 45

 Priority Encoder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 46

 4.10.Multiplexers
 A multiplexer is a combinational circuit that
selects binary information from one of many
input lines and directs it to a single output line.
 The selection of a particular input line is
controlled by a set of selection lines
 Normally, there are 2n input lines and n selection
lines whose bit combinations determine which
input is selected

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 47

 4.10.Multiplexers

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 48

 4.10.Multiplexers

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 49

 4.10.Multiplexers

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 50

 Make a 4x1 Multiplexer
using two 2x1 Multiplexers

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 51

 Verilog Modules of Combination Logic

 Gate-level modeling using instantiations of

predefined and user-defined primitive
gates.
 Gate-level (structural) modeling describes a
circuit by specifying its gates and how they are
connected with each other.

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 52

 Verilog Modules of Combination Logic

 Dataflow modeling using continuous

assignment statements with the keyword
assign .
 Dataflow modeling is used mostly for
describing theBoolean equations of
combinational logic.

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 53

 Verilog Modules of Combination Logic

 Behavioral modeling using procedural

assignment statements with the keyword
always .

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 54

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 55
 Gate-Level Modeling

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 56

 Ripple Carry Adder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 57

 Three-State Gates

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 58

 Dataflow: Two-to-Four Line Decoder

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 59

 DataFlow

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 60

 Dataflow: Conditional Operator

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 61

 Behavioral Modeling

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 62

 Behavioral Modeling

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 63

 TestBench

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 64

 TestBench

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 65

CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 66
CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 67
CEN - 220 Copyright © 2013, Bahria University. All rights reserved. 68