PROTYPING AND EMULATION

Prof B Abdul Rahim, AITS, Rajampet 1

• ASICS will continue to grow increasingly complex
• Errors of specifications, design and
implementation are unavoidable
• Designers need validation methods & tools to
ensure a perfect design before the production is
started.
• Errors caught after fabrication-
– add to production costs
– Delay in product delivery
“FIRST-TIME-RIGHT-SILICON” –goal of chip design
projects

Prof B Abdul Rahim, AITS, Rajampet 2

There are four methods to reach the goal of
First-time-right-silicon:
1. Specification on high levels of abstraction
followed by automatic synthesis
2. Simulation on various levels
3. Formal verification
4. Prototyping and emulation

Prof B Abdul Rahim, AITS, Rajampet 3

• Increased no of RTL synthesis
– Design entry at high level is increased
i.e, different hardware partitions can be implemented as
fast as software can be compiled into machine code
• More compact description results in a much
faster simulation
• CAD vendor synopsys reports
Design effort may be reduced by a factor of 10
Area & delay could be reduced by 10-20% compared to
manual designs

Prof B Abdul Rahim, AITS, Rajampet 4

• Simulation has many advantages but likely to
remain the standard technique for design
verification
• On the other hand it is time consuming
– slower than the system itself
– requires an explicit model of its test bench – costs
– Simulation very difficult with interface
components and custom components
May be treated as “Hardware in the loop” concept

Prof B Abdul Rahim, AITS, Rajampet 5

Design flow

Prof B Abdul Rahim, AITS, Rajampet 6

• As a result of these formal verification becomes important
• Two types of formal verification to be distinguished:
– Spec debugging (“did I specify what I want?”)
– Implementation verification (“did I implement what I specified?”)
• Major restrictions:
– High complexity of verification procedures of simple design modules
– Difficult to include time-related constraints into verification process
– Difficult to include an environment

FIRST-TIME-RIGHT-SILICON goal achieved by increased use of

Emulation and Prototyping
i.e coupling with real hardware – in particular with standard
microprocessors which run parts of a total software

Prof B Abdul Rahim, AITS, Rajampet 7

 PROTOTYPING AND EMULATION
TECHNIQUES
• Validation in hardware/software co-design has to solve
two major problems
– Appropriate means for SW & HW validation are needed
– These means must be combined for integrated system
validation
• Main application for HW validation are simulation,
emulation and formal verification
– Simulation provides all abstraction levels from the layout
level upto the behavioral level
– Formal verification of behavioral circuit specifications can
be processed by small & very simple subset of VHDL
– All these validation & verification are harder to implement
during HW/SW co-design.

Prof B Abdul Rahim, AITS, Rajampet 8

• Low level validation methods are not really useful, since HW/SW
co-design aims at automatic HW & SW design starting from
behavioral specifications.
Like write in c++ & debug in assembly code
• Though simulation can operate at the algorithm level, but there are
some problems too
– Simulation is very time-consuming
i.e, impossible to simulate bigger systems consisting of HW & SW parts
– Simulation is too slow to bring components work
Solution: use emulation and prototyping
 Emulation is only 100 times slower than real time
 Integration of the environment is much easier
 High expenditure for generation of test benches can be avoided

Prof B Abdul Rahim, AITS, Rajampet 9

• Today emulation is the standard technique for CPU
design & is increasingly used for ASIC design
• Emulation can become essential part of co-design
methodology
Disadvantage of emulation is its timing errors are hard or
impossible to detect.
slow compilation- once the circuit changes, different
design flows for implementation and emulation, and
the high expenditure
Solution: it is possible to overcome many of these
disadvantages by not restricting emulation to the gate
level – aiming at abstract levels.

Prof B Abdul Rahim, AITS, Rajampet 10

Ex: sun microsystems – uses emulation - design of ultrsSparc
architecture
– Speed 500,000 cycles per second
– Possible to test the boot sequences of solaris or emulate at the same
speed – start & use of windows systems such as openwin etc,
– Problem is integration of memory
– Side effect is emulation cost is very expensive
50% before first silicon & 50% after first silicon
– Complete emulation system allows improvement of fault diagnosis in
case still errors in the implemented chip
– Without emulation it would have been impossible to make complete
operating system tests, to simulate input/output behavior and to
integrate finished ASICs step by step into the total system
– The emulated components are gradually substituted by real chips

Prof B Abdul Rahim, AITS, Rajampet 11

• This allows a complete validation at any point of
the development time
– Some designers use emulations only after thorough
simulations so that no. of errors are less
– Simulations mainly aim at the reduction of no. of
functional and timing errors
– Whereas emulations aim to serve realistic loads in
demonstrating functional correctness.
• Some of the problems are caused by different
design flows required for implementation and
emulation

Prof B Abdul Rahim, AITS, Rajampet 12

Different design flow integrations for emulation

Prof B Abdul Rahim, AITS, Rajampet 13

1. Still common,; cycle simulation – no errors –
translate to ASIC
DISADV: migration from emulation results to ASICs
2. Synthesis for emulation is implemented
errors bring on changes in VHDL source
then synthesized to implemented on ASIC

Prof B Abdul Rahim, AITS, Rajampet 14

• Today existing emulation systems are
distinguished into FPGA based and custom
based solutions
• Off the shelf FPGAs and FPGAs based specially
for emulation
Xilinx XC3000/XC4000 –
Superiority is static RAM based implementation
Which allows unlimited programmability
Prof B Abdul Rahim, AITS, Rajampet 15
Prof B Abdul Rahim, AITS, Rajampet 16
PROTOTYPING AND EMULATION ENVIRONMENT
• Many different approaches for prototyping
architectures.
• Most address-prototyping of HW but not of
embedded systems
• Until now there is no integration of
microprocessors for the execution of the
software parts supported
1. Integration facilities are not flexible enough to
adequately support prototyping in HW/SW Co-
design
– In particular difficult for emulator’s synthesis SW to
route buses
Introduced by the integration of microprocessors
Prof B Abdul Rahim, AITS, Rajampet 17
1. HW partitioning is too inefficient, leading to
inadequate utilization of the emulator’s HW
resources.
2. Debugging facilities are not sufficient
Solution: FPGAs are growing faster and they are
capable of integrating more & more gate
functions and support flexible emulation
systems

Prof B Abdul Rahim, AITS, Rajampet 18

• A logic design is mapped on an emulation
board with multiple FPGAs
• Different integration schemes support the
interconnection of these multiple FPGAs.

Prof B Abdul Rahim, AITS, Rajampet 19

Principal structure of an FPGA based emulation

Prof B Abdul Rahim, AITS, Rajampet 20

• Based on interconnection structures
emulation systems with FPGAs differ
• The systems which are available on FPGAs
may be arranged in three classes
– Some systems also use programmable gate arrays
for their interconnection call structure
– Others use special interconnect switches
– Some apply especially developed custom
interconnect chips for the connection of individual
FPGAs
Prof B Abdul Rahim, AITS, Rajampet 21
 Difference between prototyping & emulation

• Prototype refers to a special architecture which is cut

to fit a specific application
– This is based on FPGAs and describes the simulation in the
programmable logic of the system which is to be designed
– However interconnection structures as well as gate
capacities of the prototype are often tuned in to the
evolving system.
– The best elements for the application can be selected -
RAMs, µc, special components etc can be used.
– Its weak point is that new expenditure occurs for every
new prototype
Some kind of compromise has to be done

Prof B Abdul Rahim, AITS, Rajampet 22

 The weaver prototyping environment
• Especially designed for prototyping in the domain of
HW/SW co-design
• It is a modular and extensible system with high gate
complexity
• It uses a hardwired regular interconnection scheme
– Fewer signals have to be routed through programmable
devices, which results in better performance
• It will not always be possible to avoid routing of signals
through the FPGAs
– This must be minimized by the supporting software
• For the interconnection of modules bus modules are
provided.

Prof B Abdul Rahim, AITS, Rajampet 23

 The weaver prototyping environment
• These offer 90-bit-wide datapaths
– Enough for 32 bit processors, that are integrated
• Depending on the type of Xilinx FPGAs used, it
provides 20k to 100k gates per board.
• Application specific components & standard
processors can be integrated via same
interfaces as the other modules

Prof B Abdul Rahim, AITS, Rajampet 24

 The weaver prototyping environment
For debugging:
 It is possible to trace all signals at run time
 To read the shadow registers of the FPGAs
 To read back the configuration data of any
FPGA in the system
 Ability to reconfigure FPGAs at runtime
without effecting other parts of architecture

Prof B Abdul Rahim, AITS, Rajampet 25

The base module

Prof B Abdul Rahim, AITS, Rajampet 26

• It carries four Xilinx FPGAs for the configurable logic.
• Each side of the quadratic base module has a connector with 90
pins
• Each FPGA is connected with one of these connectors
• Also every FPGA has a 75 bit link to two of its neighbors
• A control unit is located on the base module
• It does the programming and readback of the particular FPGAs
• A separate bus comes to the control unit of each base module in
the system
• The programming data comes via this bus serially
• The ROM is used to store the configuration data for each FPGA of
the base module

Prof B Abdul Rahim, AITS, Rajampet 27

• An IO module provides a connection to a host.
• Several interfaces are available
• With such a module the host works as IO
processor which offers an interface for
interaction to the user.
• Request of other modules must be routed
through the FPGAs of the directly connected
base module.
– This is possible but time consuming

Prof B Abdul Rahim, AITS, Rajampet 28

• This architecture can be used to build
multiprocessing systems with an arbitrary
structure.
• The structure depends on the application
which is prototyped.
• After the HW/SW partitioning the resulting
behavioral HW description has to be
synthesized via existing high level synthesis
tools.

Prof B Abdul Rahim, AITS, Rajampet 29

 EMULATION SYSTEMS

• The five most important emulation systems

are manufactured by the Quickturn, Mentor,
Zycad, Aptix and Synopsys.
– Except the synopsys all are based on off-the-shelf
FPGAs.(they essentially depend on complicated
and lengthy configuration process)
– Whereas synopsys(Arkos) and quickturn(CoBalt)
are based on special processor on which design is
mapped by a compiler

Prof B Abdul Rahim, AITS, Rajampet 30

The FPGA configuration process

Prof B Abdul Rahim, AITS, Rajampet 31

• All these emulation systems can operate in two operation
modes
a) By means of a host system, individual stimuli are applied to
an emulator in a test vector mode (the resulting test answers
are evaluated)
b) The emulated system in the target environment is operated
in a dynamic mode.

Prof B Abdul Rahim, AITS, Rajampet 32

– A logic analyzer is controlled by the emulator and
connected to the communication signals between
the emulator and the target environment.
– The logic emulator traces the signals and allows
the later analysis of this trace.
– The size of the trace buffer is very critical and
distinguishes the different emulation systems.
– It provides flexible integration of µcs, µps or DSP
cores.
– Flexibility is also required in several other areas

Prof B Abdul Rahim, AITS, Rajampet 33

• Flexibility is required in implementing large
memory blocks, which are required for both
program and data elements of the software
– This is particularly important in co-design applications.
• The clock must run as fast as possible to allow for
dynamic testing and for validation in real time
within the system-under-design
– High gate capacity
– High observability of internal nodes
– Ability to readback information out of FPGAs
– Ability to create long signal traces are also important

Prof B Abdul Rahim, AITS, Rajampet 34

 Quickturn emulation systems
Quickturn offers three different kinds of emulation systems
The smaller version is less complex described below:

Prof B Abdul Rahim, AITS, Rajampet 35

Prof B Abdul Rahim, AITS, Rajampet 36
Realizer hardware architecture

Prof B Abdul Rahim, AITS, Rajampet 37

 Mentor SimExpress emulation system
• Consists of FPGAs
– Special full custom architecture
– Developed by french co, META SYSTEMS
– 100 times faster than off-the –shelf FPGA based emulators
– Support on-chip logic analyzers
– Supports high speed fault simulation
– Higher emulation clock – 20MHz max [typically 500 khz to 4Mhz]
– 1.5 million user gates plus memory mapping
– Four different card types available – plugged in to universal slots
• Logic card [ 10k-12k user gates]
• I/O card [336 pins]
• Memory card [64Mbytes]
• Stimulus card [12 Mbytes]
– A test vector and dynamic mode are supported
• Test vector supports interactive debugging using logic analyzer
• Dynamic mode traces and triggers are used

Prof B Abdul Rahim, AITS, Rajampet 38

 Zycad paradigm RP and XP
• Paradigm XP
– Accelaration of gate level logic simulation & fault simulation
• Paradigm RP
– Based on Xilinx FPGAs / Gatefield FPGAs - GF100K
PARADIGM XP
• Seen as family of application specific supercomputers, optimized of logic and fault
simulation
• Supports accelarated logic simulation with 10 million events/second
• Supports accelarated concurrent fault simulation and mixed level simulation
• Supports upto 16 million gates logic simulation
• Supports upto 4 million gates for fault simulation
• The back annotation is supported via the standard delay format (SDF)
• The concurrent fault algorithm allows a max of 16 faults/simulation pass
– 16 times faster than a serial algorithm running on a accelerator
• Super fault SW supports 1000s of faults/pass and fault simulation of large circuit
designs and complex systems but requires more memory

Prof B Abdul Rahim, AITS, Rajampet 39

PARADIGM RP
• SW – concept silicon support prototyping and emulation
• Consists of a mother board and daughter board
architecture [RP2000 system]
• Uses backplane with xilinx 3090 FPGAs to create a crossbar
interconnection
• The backplane includes a removable prototyping board for
target system interconnect & for bread boarding on the
prototype itself
– Contains connectors for the logic analyzer interface
• Special features are incremental compilation, memory
compilation and partitioning enhancements.

Prof B Abdul Rahim, AITS, Rajampet 40

Prof B Abdul Rahim, AITS, Rajampet 41
Prof B Abdul Rahim, AITS, Rajampet 42
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 Aptix prototyping system
• Based on Aptix switches called field
programmable interconnect components
(FPICs)
– Special switches – can be programmable
- supports routing of signals between the chips of boards
– Have 1024 I/O pins arranged in 32x32 matrix

Prof B Abdul Rahim, AITS, Rajampet 44

Prof B Abdul Rahim, AITS, Rajampet 45
New versions of Aptix prototyping system
supports (MP4 system & MP4Pro system):
• Integration of shelf components & FPGAs of
any type
• Test vector & dynamic mode
– Test vector 544 probe points for debugging
available
– 288 pattern generation channels available

Prof B Abdul Rahim, AITS, Rajampet 46

Prof B Abdul Rahim, AITS, Rajampet 47
Future developments in emulation and
prototyping
• Advances of design automation enables synthesis of designs from
higher levels of abstraction
• Advances in synthesis have natural consequences for emulation,
which may lead to problems – connected with debugging
• It is very hard to keep the interrelation between description by
designs and the final emulated circuit
Solution : source level emulation (SLE)
closing the gap between description or simulation on behavioral
level and hardware emulation
• Basic idea – retention of a relation between HW elements and
source program
• It is important in HW/SW co-design and co-emulation so that
debugging implementation possible independently for HW/SW
• Debugging on the same level and with the same user interface

Prof B Abdul Rahim, AITS, Rajampet 48

Both actions, the sharing of components and sharing of registers
add muxes to the circuit

Prof B Abdul Rahim, AITS, Rajampet 49