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Line
Command
1L 3R 2L Safe
Safe Locked 1/3 Unlocked 2/3 Unlocked
Unlocked
Sound Alarm
Start
stop
success finished
stop
pause
Running Pausing
resume
hiccup events
no events events
Executing
t3 P3 P4
t3 P3 P4
t3 P3 P4
Sufficient
Funds
Card in
Slot
Sufficient
ATM Cash
IN = Input of Process
OUT = Output of Process
CR = Critical Region
SEM = Semaphore
OUT1 OUT2
OUT1 OUT2
OUT1 OUT2
OUT1 OUT2
OUT1 OUT2
t1 t2
t3 t4
t1 t2
t3 t4
s
s > 0
transition s-1
predicate p token
value
3
p s
arc
true s+1 expression
p
s
s > 0
transition s-1
predicate p token
value
3
p s
arc
true s+1 expression
p
p s
arc
true s+1 expression
p
p s
arc
true s+1 expression
p
true Maria
(MR,
Developer) (MR, (MR,
11,Tony Developer)
Developer)
7,Tom true 8,Olga
true Maria
(MR,
Developer) (MR, (MR,
11,Tony Developer)
Developer)
7,Tom true
Assigned MRs Completed MRs
Software Design (Behavioral) © SERG
Higraphs and Statecharts
Q Q^R R
P^Q^R
P^Q P^R
C F
G
J H
P
K I
O Q
S
L
T R N
M
E
Software Design (Behavioral) © SERG
Formal Definition of a Higraph
H = (B, , , E), where
e f/g F
n g
C G e
H m/e
I J
n/f
parked
stacked
landing taxiing
approach
touch down
Software Design (Behavioral) © SERG
State Chart Describing a
Computer
Computer
CPU Main Memory
Fetching
Instruction Waiting
for Request
instr. instr.
cmpl. avail. Put
Addr. Data Data Get
Written Read Addr.
Execution
Instruction
Memory Memory
Write Cycle Read Cycle
getAddr putAddr
Software Design (Behavioral) © SERG
Display State of Digital Watch
displays
update
date
hour min b
c d
c d
c
sec c time
date c a
a
a alarm
stopwatch
b c
up-alarm
c
hour sec
2-min min
[not in(stopwatch)] c c
stopwatch
d zero
[in(off)]
b b
disp run
reg on
d
d b b
[in(on)]
lap off
alive
main power
on off
b-up
alarm-state
beep-rt t-hits-tm d[in(alarm)]
[in(enable)]
beep enable disable
d[in(alarm)]
on off
stopwatch
zero a alarm
d
b b b c b-up
disp run
reg on up-alarm
d d b b hour c sec
alarm-state d[in(alarm)]
lap off
c min c
enable disable
t-hits-tm
beep-rt beep
[in(enable)] d[in(alarm)]