DSP Architectures

PRESENTED BY – SUDHANSHU JAIN (16BEE0151)

SIDDHANT NAGAR (16BEE0407)
 DSP Architectures

Harvard Architecture

The Harvard architecture requires two memory buses.

For example – DSP using 32 bit words and 32 address space requires at least 64 pins for each
memory bus - a total of 128 pins.

If Harvard architecture is brought off the chip , it results in a very large chip which are difficult to
design into a circuit.
DSP Architectures

Von Neumann Architecture

The von Neumann architecture only uses a single memory bus.
Which makes it relatively cheaper and requiring less pins so programmer
can place instruction or data anywhere throughout the available memory.
It does not permit the multiple memory access.
The modified von Neumann architecture allows multiple memory accesses
per instruction cycle by running the memory cycle faster than the
instruction cycle.
DSP Architectures

Von Neumann Architecture

Each instruction cycle can be divided into multiple ‘machine states’ and a
memory access can be made in each machine state, permitting memory
access per instruction cycle.

The Modified von Neumann architecture permits all the memory accesses
needed to support addition or multiplication: fetch of the instruction; fetch
of the two operands and a storage of result.
Why use architectures for DSPs …

Unique DATA pattern

Bit reversed addressing (FFT)
Multiple memory access
Math operation focus
Streams of data requiring high bandwidth
ALU with 16-bit operands and 32-bit result
Specialized peripherals on the board
Classification of current DSP Architecture

Modern Conventional DSPs

Similar to original DSPs of the early 1980s
Single instruction cycle. Example – TI TMS320C54x

Enhanced Conventional DSPs

Parallel execution units
Complex and Compound instructions. Example – TI TMS320C55x

Multiple – Issue DSPs

VLIW Example – TI TMS320C62xx , TI TMS320C64xx
Superscalar , Example – LSI Logic ZPS400
A conventional DSP - TI TMS320C54x

The ’54x DSPs use an advanced, modified Harvard architecture that maximizes
processing power by maintaining one program memory bus and three data memory
buses.

These processors also provide an arithmetic logic unit (ALU) that has a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-
chip peripherals.

Separate program and data spaces allow simultaneous access to program instructions
and data, providing the high degree of parallelism. Two reads and one write operation
can be performed in a single cycle.
TI TMS320C55x

TI TMS320C55x is based on earlier 54xx family but adds significant improvement to

its architecture and instruction set –

Two Instructions/ cycle –

Instructions are scheduled for parallel execution by the assembly programmer or
compiler.
Mixed – Width instructions with 8 bits to 48 bits
Complex and compound instructions
200 MHz @ 1.5v
TI TMS320C62x

This device is based on the high-performance, advanced very-long-

instruction-word (VLIW) architecture developed by Texas Instruments (TI),
making the C6204 an excellent choice for multichannel and multifunction
applications.
With performance of up to 1600 million instructions per second (MIPS) at a
clock rate of 200 MHz
This processor has 32 general-purpose registers of 32-bit word length and
eight highly independent functional units.
Program memory consists of a 64K-byte block that is user-configurable as
cache or memory-mapped as program space.
TI TMS320C64xx

Ti TMS320C64xx has 64 32-bit general- purpose registers, twice as many as

its predecessors
The instruction set is a superset of that used in previous DSPs and among
other enhancements , adds significant processing capabilities –
8 – bit operations for image/video processing
600 MHz clock speed with Dynamic caches

The only DSP family with compatible fixed and floating point versions
Very Long Instruction Word (VLIW)

VLIW describes the computer processing architecture in which a

language compiler or pre processor breaks program instruction
down into basic operations that can be performed by the
processor parallel manner.
It consists of multiple independent operations grouped together.
Each operation in the instruction is aligned to a functional unit.
Pipeline Architecture

Pipeline architecture is a parallel operation which enables every

component of the hardware to continue working at every
instance.
In pipeline there is a synchronous attempt of executing the
command.
Pipeline enables the continuous workflow, hence reducing the
time limit.
cntd…
Comparison between Parallel and serial Processing

Parallel
In parallel processing every
hardware component is at
work at every instance of time
The efficiency is more than
the serial processing.
It consists of different stages
such as 1,2 3 etc
Serial
In serial processing the next
step is defined only when the
previous step is finished.
The time taken to complete
the task is much more than of
parallel processing.