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Some of the predefined data types in VHDL are: BIT, BOOLEAN and
INTEGER.
Cont…
• The STD_LOGIC and STD_LOGIC_VECTOR data types are not
built-in VHDL data types, but are defined in the standard logic
1164 package of the IEEE library.
• We therefore need to include this library in our VHDL code
and specify that the STD_LOGIC_1164 package must be used
in order to use the STD_LOGIC data type:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY andgate IS
PORT ( a : IN std_logic; b : IN std _ logic; c : OUT std _ logic );
END andgate;
Cont…..
Enumerated Types:
– BIT ('0','1')
– BOOLEAN (false, true)
– STD_LOGIC ('U','X','0','1','Z','W','L','H','-') where: