Digital Controller For Power

Electronic Systems

Renji Chacko, Scientist ‘D’

Power Electronics Group

CDAC (formerly ERDCI), Thiruvanathapuram.

Web Site: www.erdcitvm.org
Emergence of Power Electronics Systems

Applications
DC drives, AC drives, UPS systems
Automotive applications - EV, HEV
Non conventional energy converters
- Solar, wind etc.
Power quality systems
- STATCOM, Harmonic compensators
Vector control techniques for AC systems
Implemented with digital controller
 Control Hardware

Analog Controller
Discrete Digital Logics
PLCS
FPGAS, ASICS
Micro-Controller
Digital Signal Processor

Hardware Selection depends on

Application, Circuit complexity, Speed,
Accuracy
 To Summarize on Analog
Controller

Susceptible to EMI
High band-width Sensitive to Component
aging
Advantages

Limitations
High resolution
Sensitive to
Easy to design Temperature
Simple circuit for Hardwired Design
small systems Limited to Classical
Control System
Design
 Digital Systems

Data Processing Control Application

Large memory Minimum memory
Data storage No external data storage
High level user interface Minimum user interface
Keyboard/ display Keypad and LCD display
interface Industrial fieldbus
Standard networking networking
Data processing delay Computational delay
acceptable critical
Non real time Real time
 Functional Requirements of a
Digital Controller

CPU Arithmetic and logic operations, 16-bit

TIMER Sampling Intervals and Delays
INT. Interrupts for Real Time Control
Functions
Elements

USART Serial to Parallel and Parallel to Serial

Conversion and Transmission
ANALOG
IN 12-bit, Fast Conversion, Current Driven
OUT
8/12-bit Data for Display
DIGITAL
IN Optically Isolated
OUT
Optically Isolated, Transistor/Relay Driven
 Digital System for Control
Applications
WDT
WDT MEMORY
MEMORY UART
UART RS232C
RS232C

DATA BUS 8888

ADDRESS BUS
80188
80188 KEY
CONTROL BUS
CPU
CPU BOARD

ADC
ADC DAC
DAC DIGITAL
DIGITAL
I/O
I/O
OPTICAL
OPTICAL
ISOLATOR
ISOLATOR
SIGNAL ANALOG TRANS
TRANS
SIGNAL RELAY
CONDITION OUTPUTS OPTICAL
OPTICAL RELAY
CONDITION ISOLATOR
ISOLATOR

ANALOG DIGITAL DIGITAL

INPUTS INPUTS OUTPUTS
 The CPU 16 bit CPU with
2 Timers
Interrupt
Data Controller
clock Bus Data Bus 8-bit
20 bit Address
Int. address
Bus Control lines for
Read, write, etc
control 80C188
80C188 control
Clock 24MHz
in Bus
Control for DMA,
Tim Timer etc
out Internal Decoders
I/o Built-in I/Os
cs
 To summarize on Micro-Controller

Large Dynamic Range

Creates Numerical

DISADVANTAGES
Insensitive to Time
Patterns in an Analog
ADVANTAGES

and Temperature
World
Common Hardware
Minimum Hardware
for many Applications
even for Simple
Algorithmic
Applications
Implementation
Design is Time
Repeatable
Consuming
Remote Computer
Computational Delay is
Interface
Critical
Self Diagnostics
DIGITAL SIGNAL PROCESSOR (DSP)
FOR
REAL TIME CONTROL
 Real Time Control

Reacts in deterministic way

Several tasks executed concurrently
 Comparison between
DSP and Micro-Processor

High Performance On-chip Peripherals

Signal Processing Supervisory functions

Micro-controller
Architecture Familiar Architecture
Advanced Control
DSP

Techniques
Additional functions Low Performance
Computation Delay
Numerical Problems
Limited Peripherals
 Architecture of TMS320F206 DSP

D/P RAM D RAM D/P RAM P FLASH A(0.15)

256x16 288x16 4Kx16 32Kx16 D(0.15)

I/O
CPU
64Kx16
16-Bit TREG
16-Bit x 16-Bit Multiply Software
32-Bit PREG WSG
ShiftL
Timer
32-Bit ALU
32-Bit ACC
Serial Port
8 Auxiliary Registers
(sync)
8 Level Hardware Stack
Repeat Instruction Counter Serial Port
2 Status REG (async)
 DSP
Features

Features Benefits
Single Cycle Instruction Advanced Algorithm
Pipelined Architecture High Band Width
Harvard Architecture Parallel Data & Program
Hardware Multiplier Min. Computation Delay
Hardware Shifters Large Dynamic Range
16-Bit Word Min. Quantization Errors
32-Bit Registers Min. Truncation Error
Hardware Stack Fast Int. Processing
Saturation Mode Prevents Wrap-Around
Built-in Timer, Wait State, Minimize Hardware
Serial I/O
 Comparison between Floating Point
and Fixed Point Digital Controllers

Less Expensive
Programmable
Less Hardware
Software Development
Floating Point

Fixed Point
Cost Low
Software
Development in High
Development Cost High
Level Language
Truncation and
Overflow Errors
Effective codes
Expensive and Costly through Assembly
Components Language
Real time DSP Controller for
PE

Clock Reset Fault

Interlock

Analog Gate Signal

Sensors Gate Driver
Interface Generation
DSP

( AC Drive FPGA
Algorithm )
User Digital Analog output
Interface Logic (Debug)

Serial
Development Network
JTAG Interface
System
Interface
DSP based PE Controllers

Stand Alone Small Systems

for UPS, small AC Drives etc.
Stand Alone Medium Power
Systems
for Industrial Drives, UPS
etc.
PC Based Controller
for large systems.
 Stand Alone Small
Systems

Ref. To Gate
Isolation CPU FPGA Ckt
Timer
Int.
P Flash
Fb.
RAM Fb.
RS232C ADC
USART Ckt

TxD
RxD
DSP Circuits for
PE
STANDALONE CONTROLLER WITH SMPS
Stand Alone Medium Power
Systems

To
AD
DP DSP Gat
C
RAM Ckt e
DA CPU s
C
Digital
I/O

RS232C
888888
RS485
STANDALONE CONTROLLER WITH
NETWORK
 PC Based Controller
Features
 Standard Hardware
 One PCB PE Specific
 Upto to date Hardware
PCBs  Cost High
On PC MB  All software resource
easily adaptable
 Fast development
Industrial PC
All PC Elements such as PC SMPS, FDD, HDD,
VDU, Keyboard, Mouse Used during design
FDD, VDU, Keyboard, Mouse Removed
SMPS by small one and HDD by Flash Replaced
 PE Specific Hardware on
PC

DSP To
888888 Ckt Gat
s e

DP
RAM

I/O
PC
interfa
Bus
ce DP DSP To
RAM Ckt Gat
s e
PC Add-on System
Control Hardware Flow Diagram
 Digital Controller Hardware
Features

Multi layer PCB with Dedicated digital and ground planes

On board digital power supply regulator
Proper isolation from power circuit
Proper placement/ shielding to reduce EMI/EMC effect
Placement of components :
No mixing of high frequency
low frequency/ analog signals
Local decoupling for digital circuits
Isolation for I/O signals
 Design Techniques for
EMC

Most preferred techniques

 Circuit design and choice of components

 Cables and Connectors

 Filters and Transient suppressors

 Shielding

 PCB layout

 ESD, Electromechanical devices and PFC

Circuit design and choice of
components

 Digital components and circuit design

Choosing components,Bad IC sockets,
Spread spectrum clocking
 Analog components and circuit design

Choosing components, Preventing demodulation problem

 Switch-mode design

Topology,Snubbing,Heat sinks, Rectifiers, Magnetics

 Signal communication components and circuit design

Non-metallic communication,Optoisolation,
Communication,Protocols
 Choice of passive components
Distributed Control Architecture

Asyn link

Syn link

Drive1 Actuators
Actuators
Drive1
Sensor
Sensor
Drive
Drive 22 Elements
Elements 11

…. …..
Sensor
Sensor
Drive
Drive nn Elements
Elements nn
 Controller Networking
Mod Bus
Address Function Data Checksum EOF

Address Is the Address of the Controller

Function M-to-S, S-to-M, 16-bit, 8-bit, Variable or logic
Data Address, no of data, data
Checksum If no error acknowledge or skip

Master – Slave configuration

Message oriented protocol
Can be implemented on standard hardware like RS-232, RS-485
 Mod Bus Protocol
Master

Slave 1 Slave 2 Slave n

Query
Update a variable value
Master Slave
Acknowledge
Response
(Value updated)
Data exchange in write mode
Query
Read a variable value
Master Slave
Value of the variable
Response

Data exchange in read mode

 Controller Area Network(CAN)
S R I A I
Idle O Identifier T D r0 DLC Data CRC C EOF F Idle
F R E K S

Message Frame Format

CAN efficiently supports distributed real-time control applications
 Producer/Consumer broadcast model
 Prioritization of messages, message identifiers instead of node address
 Configuration flexibility
 High reliability , Error detection and signaling
 Automatic retransmission of corrupted messages.
 Autonomous switching off of defect nodes
Carrier-sense, multiple-access-with-collision-resolution (CSMA/CR) protocol
Non-destructive bit-wise arbitration
Message oriented broadcast communication
CAN Protocol
 Digital Controller for
Automotive Application
PC

3.3 V JTAG RS232

12V Processor based CAN CAN

Controller interface Bus
SMPS

14V DC 15V, 5V
Bus
(Optional) 42V Peripheral Interface GATE
42V DC drive
SMPS
Bus

Digital Analog GATE

I/O I/O Signals
 System Design

 Formulate the Specification

 Develop the Overall Block Diagram
 Develop the Control Block
 Develop the Flow Chart
 Develop the Flow Diagram
 Select an Appropriate Hardware
 Develop the Functional Software Modules
 Appropriately Cascade the Functional Modules
 Scale and Debug
Common Software Functional
Modules

• Digital/ Analog input interface

• Space vector PWM
• PID controller
• d-q Transformation and Re-transformation
• 3–phase to 2–phase transformation and vice versa
• Machine model implementation
• Calculation of machine torque
• Calculation of speed
• Calculation of stator flux
• Delay elements
• Integrator
• Sin and cos function generators
•Digital/ Analog output interface
 Functional Module Identification
Look up table based function input output
f(n)
generator

Integrator
t = kts 0 kts
u (kts ) = ∫ e(t )dt = ∫ e(t )dt + ∫ e(t )dt
t = −∝ −∝ 0
input output

u (kts ) = u[(k − 1)ts ] + Ts * e[kts ]

Delay element

input output
du (t )
Td + u (t ) = e(t )
dt
u (kts ) = u[(k − 1)ts ] + [(Ts Td ) * {e(kts ) − u (k − 1)ts}]
 Functional Module Identification

PI controller

u (t ) = kpe(t ) + ki ∫ e(t )dt input output

u (kts) = kpe(kts ) + ki ∫ e(kts )

3-Phase to 2-Phase conversion

isα (kts ) = 1.5 * isr (kts ) input 3φ output

2φ
isβ (kts ) = ( 3 ) * [isy (kts ) − isb(kts )]
2

d-q transformation

isα (kts ) = [isd (kts ) * cos(kts)] − [isq (kts ) * sin(kts )] input 2φ output

isβ (kts ) = [isd (kts ) * sin(kts )] + [isq (kts ) * cos(kts )] d-q

 PI Controller Equation

u (t) = K P . e (t) + K I . ∫ e(t) dt S =

T
2
( z +1
z −1
)
K
I
U (s) = K P . E (s) + . E (s)
S

U (z) = K P . E (z) + K I . E (z).

T z + 1 

z − 1 
.
2

T
U (z). ( z − 1) = K P . E (z). ( z − 1) + K I . E (z).
.( z + 1)
2
−1 −1 T −1
U (z). (1 − z ) = K P . E (z). (1 − z ) + K I . E (z). .(1 + z )
2
 PI
Controller Equation cont..

U (z) = U (z).z
− 1
+ (K P
). E (z) + ( − K + K
+ KI .
2
T
P I
.
T
2
). E (z).z − 1

U = U + (K P
+ KI . ). E + (− K + K . ). E
T
2 P
T
2 I
− 1 − 1

u (k) = u (k − 1) + (K P
+ KI .
T
2
). e(k) + ( − K P
+ KI .
T
2
). e(k − 1)
u (k) = u (k − 1) + K 1 . e (k) + K 2 . e (k − 1)
T
K1 = K P + K I .
2
T
K 2 = −K P + K I .
2
 PI Controller Software module
piSpeed:
SETC OVM
LACC softSpeed
SUB wFb ;rotorSpeed
SACL sp0Error
* ----------------------------------------------------------
BCND negSpError,LT
SUB #kpSpeedLimit
BCND skipSpError,LT
SPLK #kpSpeedLimit,sp0Error
B skipSpError
negSpError:
ADD #kpSpeedLimit
BCND skipSpError,GT
SPLK #-kpSpeedLimit,sp0Error
skipSpError:
•----------------------------------------------------------
LT sp0Error
MPY kpSp ;e[k]*Kp
PAC
SACL tempA
PI Controller Software module
LACC torq0Error ;acc=e[k]
ADD torq1Error ;acc=e[k]+e[k+1]
SACL tempB ;tempB=e[k]+e[k+1]
LT tempB ;T=e[k]+e[k+1]
MPY kiTorq ;P={e[k]+e[k+1]}*Ki*T/2
LACL piTorqILo
ADD piTorqIHi,16 ;acc=Icon[k]
LTD torq0Error ;acc=Icon[k]+{e[k]+e[k+1]}*Ki*T/2,
T=sp0Err0r, volt1Error=volt0Error
SACL piTorqILo
SACH piTorqIHi ;Icon[k+1]
ADD tempA,16
SACH tempA

LT tempA
MPY Tmax
PAC
SACH piTorqRef,1
CLRC OVM
RET
 Structuring DSP For
Power Electronics Control

Timer Int.

Initialization
Sampling time Sampling time

Timer output
To the interrupt
Int. Routine
Main Routine
Software Development phases

PC based software development

C, C++, Assembly
Cross compiler/ assembler
Target Memory allocation for software
modules
Downloading and running in RAM
Debugging
Firmware into Flash/ EPROM
 Software development Support
Simulator –
Software programs that simulate the
operation of the processor
No target hardware required
Monitor debugger-
Serial port, RS 232C
Intel iaPX 86/88
 Software development
Support
In Circuit Emulator- Emulation processor replaces
Actual processor

In circuit Target
Emulator Board

JTAG (IEEE 1149.1)

Emulator –
PC Add on Card, Parallel port
Emulator header in target board
Trends in digital control
Hardware
Low voltage design: 3.3V instead of conventional 5V
Higher level of integration, low power, Higher speed
High End Integration
ADC, DAC, PWM - Minimize the external interface for speed compatibility
No External data/ address bus and associated control lines
Flash / EEPROM memory
Power Down features in idle and fault condition
External Lower frequency crystal
10Mhz for 40-125 Mhz
Serial interface through SPI and SCI
Minimum I/O s for interface, if any
Complete system working on Single supply
Reduced power supply requirement
Built in industrial field bus network interface
CAN, I2C
 Power Electronics Group
C-DAC
( Centre for Development of Advanced
Computing )
Thiruvananthapuram