Вы находитесь на странице: 1из 17

JTAG

IEEE 1149.1 Test Access Port


Intro
JTAG is the name used for the IEEE 1149.1 standard entitled Standard
Test Access Port and Boundary Scan Architecture for test access ports
(TAP) used for testing printed circuit boards (PCB) using boundary scan.

JTAG is the acronym for Joint Test Action Group, the name of the
group of people that developed the IEEE 1149.1 standard.
Comparison of the test methods ICT and Boundary Scan
Intro
● JTAG is defined as a serial communication protocol and a state
machine accessible via a TAP.
● The JTAG TAP controller is used for development purposes
(Boundary Scan testing, Memory BIST and debugging).
● The functionality usually offered by JTAG is Debug Access and
Boundary Scan and functions as an interface between the
processor(s),peripheral cores, and any commercial debugger/emulator
or Boundary Scan (BS) testing device.
Debugging system block diagram
WRAPPER
ARCHITECTURE
PIN Description
● A JTAG network typically has five I/O signals
● TDI (test data input): all data sent to the JTAG network goes
through the test data input.
● TDO (test data output): all data read from the JTAG network comes
out the corresponding test data output.
● TCK: Test clock input
● TRST (test reset signal ) : it is an optional test input signal
● TMS( test mode select): used for determining the test mode state of
the TAP controller
WRAPPER ARCHITECTURE
The following instructions are supported by the TAP ( Register List for IR (Instruction Register) )
TAP Controller
TAP CONTROLLER STATE
MACHINE

● The IEEE standard defines a 16-


state state machine called the TAP
controller to control several actions
● Each state of the TAP controller
can be reached by a sequence of
bits transmitted via the TMS line
depending on the current state.
TAP Controller
● When the TAP controller is in the TEST_LOGIC/RESET state,the instruction
register is initialized with IDCODE as the initial instruction.
● Forcing the TAP controller, to the TEST_LOGIC/RESET state is achieved by
holding TMS high for five TCK clock cycles, this is called soft reset of TAP
● Instruction Register path, Data register path are different, transfering from IR
path tO DR path is by TMS input
● At shift_ir state, TDI will transfer the data Instruction register value.
● At Shift_dr state, TDI will transfer the data to Data register value.
● Update_ir stage will update the Instruction register
● For Bypass operation will always have all bits of IR as high.
● TMS,TDI operate on negative clock edge, TDO operate on positive clock edge.
TAP Controller
FSM OUTPUT PINS

TMS
Thank you