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CMOS Fabrication

Syllabus
• Basic CMOS Technology:
• Self aligned CMOS process,
• N well,
• P well,
• Twin tub,
• Layout of CMOS Inverter,
• CMOS Layout and Design rules.
MOS
• A Metal-Oxide-Semiconductor (MOS) structure is
created by superimposing several layers of
conducting and insulating materials to form a
sandwich-like structure.
• These structures are manufactured using a series of
chemical processing steps involving
• Oxidation of the silicon, selective introduction of
dopants, and deposition and etching of metal wires
and contacts.
• CMOS technology provides two types of transistors
(also called devices):
an n-type transistor (nMOS) and
a p-type transistor (pMOS).
• Transistor operation is controlled by electric fields
so the devices are also called Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs)
or simply FETs.
• We can view MOS transistors as electrically
controlled switches
• Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
The four main CMOS technologies:

• N-well process
• P-well process (Similar to N-Well)
• Twin-tub process
• Silicon on insulator (Not in Syllabus)
CMOS
• Transistors are fabricated on thin silicon wafers that
serve as both a mechanical support and an
electrical common point called the substrate.
• the inverter is built on a p-type substrate.
• The pMOS transistor requires an n-type body
region, so an n-well is diffused into the substrate in
its vicinity.
CMOS Fabrication
• Lithography process similar to printing press
• On each step, different materials are deposited or
etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

Fabrication and Layout Slide 8


Inverter Cross-section
• Typically use p-type substrate for nMOS transistor
• Requires n-well for body of pMOS transistors
• Several alternatives: SOI, twin-tub, etc.
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Fabrication and Layout Slide 9


Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
• Use heavily doped well
A and substrate contacts /

taps GND Y
V DD

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

Fabrication and Layout Slide 10


Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2

p substrate

Fabrication and Layout Slide 11


Oxidation
• Grow SiO2 on top of Si wafer
• 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Fabrication and Layout Slide 12


Photoresist
• Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

Photoresist
SiO2

p substrate

Fabrication and Layout Slide 13


Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist

Photoresist
SiO2

p substrate

Fabrication and Layout Slide 14


Etch
• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

Fabrication and Layout Slide 15


Strip Photoresist
• Strip off remaining photoresist
• Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate

Fabrication and Layout Slide 16


n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si
SiO2

n well

Fabrication and Layout Slide 17


Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

n well
p substrate

Fabrication and Layout Slide 18


Polysilicon
• Deposit very thin layer of gate oxide
• < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

Fabrication and Layout Slide 19


Polysilicon Patterning
• Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

Fabrication and Layout Slide 20


Self-Aligned Process
• Use oxide and masking to expose where n+
dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

Fabrication and Layout Slide 21


N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned
gates because it doesn’t melt during later
processing

n+ Diffusion

n well
p substrate

Fabrication and Layout Slide 22


N-diffusion
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well
p substrate

Fabrication and Layout Slide 23


N-diffusion
• Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

Fabrication and Layout Slide 24


P-Diffusion
• Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

Fabrication and Layout Slide 25


Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide


p+ n+ n+ p+ p+ n+

n well
p substrate

Fabrication and Layout Slide 26


Metallization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

Fabrication and Layout Slide 27


P Well Process
• Oxidation
• Photoresist
• Lithography
• Etch
• Strip Photoresist
• Strip Oxide
• Polysilicon
• Polysilicon Patterning
• Self-Aligned Process
• N-diffusion
• P-Diffusion
• Contacts
• Metallization
Twin Tub
• Tub formation
• Thin-oxide construction
• Source and drain implantations
• Contact cut definition
• Metallization
This process provides separately optimized wells,
balanced performance n-transistors and p-transistors
may be constructed.
• It is also possible to create both a p-well and
an n-well for the n-MOSFET's and p-MOSFET
respectively in the twin well or twin tub
technology.
• Such a choice means that the process is
independent of the dopant type of the starting
substrate (provided it is only lightly doped).
CMOS Inverter
• The composition of a PMOS transistor creates low
resistance between its source and drain contacts when
a low gate voltage is applied and
• high resistance when a high gate voltage is applied.
• On the other hand, the composition of an NMOS
transistor creates high resistance between source and
drain when a low gate voltage is applied
• and low resistance when a high gate voltage is applied.
• CMOS accomplishes current reduction by
complementing every nMOSFET with a pMOSFET and
connecting both gates and both drains together.
• A high voltage on the gates will cause the nMOSFET
to conduct and the pMOSFET to not conduct, while
a low voltage on the gates causes the reverse.
• This arrangement greatly reduces power
consumption and heat generation.
• However, during the switching time, both MOSFETs
conduct briefly as the gate voltage goes from one
state to another.
• This induces a brief spike in power consumption
and becomes a serious issue at high frequencies.
• CMOS circuits are constructed
in such a way that
all PMOS transistors must
have either an input from the
voltage source or from
another PMOS transistor.
Similarly, all NMOS transistors
must have either an input
from ground or from another
NMOS transistor.
• When the voltage of input A is low, the NMOS
transistor's channel is in a high resistance state.
• This limits the current that can flow from Q to ground.
The PMOS transistor's channel is in a low resistance
state and much more current can flow from the supply
to the output.
• Because the resistance between the supply voltage
and Q is low, the voltage drop between the supply
voltage and Q due to a current drawn from Q is
small.
• The output therefore registers a high voltage.
• On the other hand, when the voltage of input A is
high, the PMOS transistor is in an OFF (high
resistance) state so it would limit the current
flowing from the positive supply to the output,
while the NMOS transistor is in an ON (low
resistance) state, allowing the output from drain to
ground.
• Because the resistance between Q and ground is
low, the voltage drop due to a current drawn into Q
placing Q above ground is small.
• This low drop results in the output registering a low
voltage.
Design Layout
• Layout design rules describe
how small features can be and
how closely they can be reliably packed in a
particular manufacturing process.
• Industrial design rules are usually specified in
microns.
• This makes migrating from one process to a more
advanced process or a different foundry’s process
difficult because not all rules scale in the same way.
Lambda Rule λ
• Mead and Conway [Mead80] popularized scalable
design rules based on a single parameter, λ, that
characterizes the resolution of the process.
• λ is generally half of the minimum drawn transistor
channel length.
• This length is the distance between the source and
drain of a transistor
• It is set by the minimum width of a polysilicon wire.
• For example, a 180 nm process has a minimum
polysilicon width (and hence transistor length) of
0.18 μm and uses design rules with λ = 0.09 μm3.
• Lambda-based rules are necessarily conservative
because they round up dimensions to an integer
multiple of λ.
• The potential density advantage of micron rules is
sacrificed for simplicity and easy scalability of
lambda rules.
• Designers often describe a process by its feature
size.
• Feature size refers to minimum transistor length,
so is half the feature size.
• below 180 nm, design rules have become so
complex and process specific that scalable design
rules are difficult to apply.
• However, the intuition gained from a simple set of
scalable rules is still a valuable foundation for
understanding the more complex rules.
• MOSIS has developed a set of scalable lambda-
based design rules.
• It covers a wide range of manufacturing processes.
• The rules describe the
minimum width to avoid breaks in a line,
minimum spacing to avoid shorts between
lines, and
Minimum overlap to ensure that two layers
completely overlap.
A conservative but easy-to-use set of design rules for layouts with two
metal layers in an n-well process is as follows:

• Metal and diffusion have minimum width and spacing


of 4 λ
• Contacts are 2 λ × 2 λ and must be surrounded by 1 λ
on the layers above and below.
• Polysilicon uses a width of 2λ
• Polysilicon overlaps diffusion by 2λ where a transistor is
desired and has a spacing of 1 λ away where no
transistor is desired.
• Polysilicon and contacts have a spacing of 3λ from
other polysilicon or contacts.
• N-well surrounds pMOS transistors by 6λ and avoids
nMOS transistors by 6λ
Simplified Design Rules
• Conservative rules to get you started

Fabrication and Layout Slide 42


Gate Layouts
• For many applications, a straightforward layout is
good enough and can be automatically generated
or rapidly built by hand.
• The “line of diffusion” rule that is commonly used
for standard cells in automated layout systems.
• This style consists of four horizontal strips:
• metal ground at the bottom of the cell,
• n-diffusion,
• p-diffusion, and
• metal power at the top.
• The power and ground lines are often called supply
rails.
• Polysilicon lines run vertically to form transistor
gates.
• Metal wires within the cell connect the transistors
appropriately.
Inverter Layout
• Transistor dimensions specified as Width / Length
• Minimum size is 4l / 2l, sometimes called 1 unit
• For 0.6 mm process, W=1.2 mm, L=0.6 mm

Fabrication and Layout Slide 45

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