DIP-Dual Inline

Package
• First package invented in 1960
with 14 leads by Bryant Rogers
• Used for low pin count (8-48)
• Not preferred when space is an
issue
• Application includes memory and
microcontroller
• Peripherally leaded package
• Pin through hole type
 SOP-Small Outline
Package

• Suited for (24-48) pins

• Used in memory packaging with
space as constrain
• Construction similar to DIP but
pins have minimal standoff
• Peripherally leaded package
• Surface mount type
QFP-Quad Flat
Package
• Lead frame runs all four sides of the package
• Peripherally leaded package
• Pin count can go up to 304
• Surface mount type
BGA-Ball Grid Array
• Belongs to area array packages.
• Pin count of (300-600).
• Short electrical interconnected path.
• Can include power and ground planes as part of BGA construct
CSP-Chip Scale Package
• Occupies a footprint area of no more than 50% greater than the area
of the chip it packages.
• has a perimeter no more than 20% greater than that of the chip it
packages.
• Major advantage size reduction.
Heat management
• In face down configuration (Flip-Chip)

1. Leads/Balls (Low power operation)

2. Thermally conductive fingers (High power

operation)

• In face up configuration

1. Conduction through substrate

 MCM
• A single unit containing two or more chip.
• High packaging density.
• Better electrical performance due to
reduced distance.
• Reduced interconnection between chip and
board(reliability).
• Cost reduction
IC Assembly

• Chip to package interconnection

1. Wire bonding
2. Tape automated bonding
3. Flip chip
 Wire bond
• Typically fine gold wire (25um)
• Wire is attached to each IO pads on
chip and its associated package pin.
• Huge industry support.
• Cost effective
Flip chip
• Method of connecting chip to package.
• High lead count.
• Simultaneous connection.
• Active face is facing the substrate.
• Low resistance, capacitance and inductance (Better electrical
property).
• Bumps provide :- electrical connection; heat dissipation path; link
between chip and substrate.
• Introduced by IBM (1962).
• Flip chip structure consists of
1. Chip
2. Substrate
3. Interconnect
Interconnection
system

• Has three parts

1. Chip bump
2. Under bump metallization
3. Encapsulation
4. Substrate metallization
 • Prevents the corrosion of
chip metallization.
• contaminants diffuse from
encapsulant.
• Compatible layer between
bump and final chip
metallization.

Under bump metallization

Components of UBM

• Adhesion layer (Cr, Ti, W,

TiW)
• Barrier layer (Cr, W, Ti, TiW,
Cr-Cu)
• Wetting layer (Cu, Ni, Pd, Pt)
• Anti-oxidation layer (Au)
UBM Layers Materials used Purpose

Adhesion layer Cr, Ti, Ni, W, TiW, Zincate Promotes strong interface between the chip metallization, the bump and
chip passivation.

Barrier layer Cr, Ti, Ni, W, TiW, Cr-Cu Prevent the diffusion of metal species and ionic contaminants into the
chip metallization and adhesion layer.
Such diffusion results in brittle intermetallic and corrosion of chip.

Wetting layer Cu, Ni, Pd, Pt Provides consumable layer for bump metallization to wet and react.

Anti-oxidation layer Au Used in order not to embrittle the UBM-bump interface by the formation
of intermetallic.
Chip passivation
• Polyimide and BCB(Benzo cyclobutene)

• Purpose
1. Protection from environment(moisture and corrosion).
2. Provides stress relief.
Underfill
• Distributes the stress over a large area.
• Stress is because of the difference in coefficient of
thermal expansion of the chip, solder
interconnection and the substrate.
• Material used silica filled epoxy.
Tape automated bonding
• the bonding sites of the die, are
connected to fine conductors on
the tape
• IC is mounted on metallized
flexible polymer tape.
• Light weight.
• Higher IO counts.