I2C Protocol Implementation: Guided By: MR .Y.V. Joshi Mr. Vaibbhav Taraate

I2C PROTOCOL
IMPLEMENTATION
GUIDED BY:
Mr .Y.V. Joshi
Mr. Vaibbhav Taraate
PRESENTED BY:
o Atul Kokate
o Ganesh wattamwar
o Omprasad Rathod
o Pranav Bobade
o Karunesh Junghare
OBJECTIVE
• Design a bus which can communicate between master and multiple slave.
• Implement bus which use a smaller number of bit for transferring 8-bit data.
• Develop a bus which uses a less number of pins for data transfer between
microcontroller and peripherals device.
• Design a bus which Eliminates the need for address decoders and Increase
system design flexibility and making simple construction.
29-07-2019 I2C BUS IMPLEMENTATION 2

WHAT IS I2C ?
I2C stands for Inter-Integrated Circuit.
Invented by Philips (NXP) in 1982.
It is also known as TWI(Two Wire Interface)

Two wires for data transmission and
synchronization.
Bidirectional Bus.
A serial, half duplex and synchronous
communication protocol

Only two bus lines SDA and SCL.
Each device connected to the bus is software

addressable by a unique address.
I2C-BUS
FEATURES Masters can operate as master-transmitters or as
master-receivers.
If multi-master initiate data transfer, then collision

detection and arbitration prevent data corruption.
29-07-2019 I2C BUS IMPLEMENTATION To be continued…. 4

Serial, 8-bit oriented,
bidirectional data transfers.
I2C-BUS On-chip filtering rejects spikes

on the bus data line to preserve
FEATURES data integrity.
The number of ICs that can be

connected is limited by a
maximum bus capacitance.
I2c has two pins namely
PINS AND 1.Serial Data Line (SDA):

FUNCTIONALITY • wire on which actual data transfer
happens.
• which is a bidirectional.
• Between different master and slaves.
2.Serial Clock Line (SCL):

• On which master device generates the
clock for slave devices.
• Which is a bidirectional.
Important element of i2c
communication.
It initiates communication with
slave.
The device that drives the SCL
I2C MASTER clock line.
Also terminate a data transfers.
Data transfer over I2C Bus is
always controlled by master.

The slaves are the devices that respond
to the master.
Element that addressed by master.

I2C SLAVES
Each slaves have their unique address.
A slave cannot initiate a transfer over

the I2C bus.

Notice that Slave 1 cannot communicate with
GENERAL CONCEPT Slave 2 or 3 (except via the ‘master’)
FOR SERIAL
COMMUNICATIONS Only the ‘master’ can start communicating.
Data, Select and R/W signals can share the

same line, depending on the protocol
An asynchronous communication does not have

a Clock signal
A point to point communication does not

require a Select control signal
Diagram for MASTER TO SLAVE COMMUNICATION

FORMAT FOR I2C COMMUNICATION PROTOCOL

Master send the START condition
Followed by First Byte which contains the SLAVE ADDRESS + WRITE BIT.
Slave acknowledges it by sending back an Acknowledge (ACK) bit to the

Master.
MASTER TO SLAVE
COMMUNICATION
Next, the Master sends 1 or more bytes to slave.
After each byte received the Slave sends back an Acknowledge bit (ACK).
When Master wants to stop writing it then sends a STOP condition.

Master sends the First Byte which contains the SLAVE ADDRESS + READ BIT
Slave acknowledges it by sending back an Acknowledge (ACK) bit to the

Master.
Next, the Slave sends 1 or more bytes

SLAVE TO MASTER
COMMUNICATION
Master acknowledges it every time by sending an Acknowledge bit (ACK).
When the Master wants to stop reading it sends a Not Acknowledge bit
(NACK)
Then master send STOP condition.

START AND STOP
CONDITION IN I2C
• A HIGH to LOW transition on

the SDA line while SCL is
HIGH defines a START
condition.
• A LOW to HIGH transition on
the SDA line while SCL is
HIGH defines a STOP
condition.
• START and STOP conditions
are always generated by the
master.

DATA VALIDITY
• The data on the SDA line

must be stable during the
HIGH period of the clock.
• The HIGH or LOW state of
the data line can only
change when the clock
signal on the SCL line is
LOW.
• One clock pulse is generated
for each data bit
transferred.

ACKNOWLEDGE (ACK) NOT ACKNOWLEDGE (NACK)
The acknowledge takes place after every byte. The Not acknowledge takes place after every byte.
The transmitter releases the SDA line during the The transmitter releases the SDA line during the
acknowledge clock pulse so the receiver can pull acknowledge clock pulse so the receiver can pull
the SDA line LOW. the SDA line HIGH.
It remains stable LOW during the HIGH period of It remains stable HIGH during the HIGH period of
this clock pulse. this clock pulse.

SPECIFICATIONS
❏ Number of Master : Single Master
❏ Type of communication : Serial(bit by bit)
❏ Direction : Bidirectional and half duplex
❏ Number of address bit for slave : 7 bits
❏ Data frame : 8 bits
❏ Number of pins used : Two pins (SDA & SCL)
❏ I2C Speed Modes : 100Kbps (Standard mode)
❏ Memory Capacity : 8 Bytes

SPECIFICATIONS
❏ Number of Slaves : Upto 112(or <112)
❏ Input & Output reference level: VIL=0.3Vcc, VOH=0.7Vcc
❏ Operating frequency : 100KHz
❏ Synchronous or Asynchronous : Synchronous
❏ There is no interrupt service.
TOP LEVEL DIAGRAM
SDA LINE
data_bus
M SCL LINE SLAVE 1
H Cmd_in
A
SLAVE 2
O S
S I2c_transmit_done
T
SLAVE 3
T E
R
reset_n
clk SLAVE 4
NAME OF DIRECTION NUMBER DESCRIPTION
SIGNAL OF BITS
SDA(Serial Data Bidirectional 1 bit Data is transferred between
DESCRIPTION line) master and slave through this line.
OF TOP- SCL(Serial Clock line) Bidirectional - The line on which clock is

generated by master device.
LEVEL
Cmd_in Unidirectional 1 bit These control signals are generated
SIGNAL by host ,which give commands as:
1. Initiate master to slave
communication.
2. Initiate slave to master
communication.
NAME OF DIRECTION NUMBER OF DESCRIPTION
SIGNAL BITS
data_bus Bidirectional 8 bits Data is transferred between host
and master through this bus.
DESCRIPTION
OF TOP- I2c_transmit_done Unidirectional 1 bits To indicate status of master following
operation:
LEVEL 1. master to slave communication.
SIGNAL 2. slave to master communication.
reset_n Unidirectional 1 bit It is asynchronous active low reset.
clk Unidirectional 1 bit It is clock input to master.

BLOCK LEVEL DESIGN: MASTER
I2C MASTER
status_bus[1:0]
FSM CONTROLLER
READ BUFFER
SIPO
READ FSM
REGISTER
H DIRECTION
CONTROLLER
O data_bus
WRITE BUFFER
PISO
SDA
LINE
WRITE FSM REGISTER
S
T SYNCHRONIZATION ACK AND NACK LOGIC BUS
control_bus[2:0]
LOGIC
COMMAND BUFFER SCL
AND LINE
reset_n DECODER
CONTROL
AND
clk TIMING BLOCK
RTL DESIGN OF WRITE BUFFER

PIN FUNCTION OF WRITE BUFFER
NO. NAME OF PINS DIRECTI NO. OF FUNCTION
ON PINS
1. d_in input 8 Input data to write buffer.

2. clk Input 1 Clock to write buffer.
3. Cmd_en Input 1 This is command enable to write buffer from host.
4. flush_in Input 1 To reset the address after operation.
5. full_in Input 1 This is signal from FSM of master to write buffer for stopping
further writing.
6. temp_in Input 1 This is for reading data from write buffer.

7. d_out Output 8 output data from write buffer.
8. full_wr_buff Output 1 It high when write buffer is full.
9. empty_wr_buff Output 1 It high when write buffer is empty.
RTL VERIFICATION OF WRITE BUFFER
Signal Operation
reset_n=1 No operation will be performed
reset_n=0, host_en=1,cmd_en=1,temp_in=1 Data can be write into write buffer
reset_n=0,full_in=1, No more write operation can be done

reset_n=0,temp_in=0 Data can be read from write buffer.

RTL VERIFICATION OF WRITE BUFFER

RTL DESIGN OF READ BUFFER

PIN FUNCTION OF READ BUFFER
NO. NAME OF PINS DIRECTI NO. OF FUNCTION
ON PINS
1. d_in input 8 Input data to read buffer.

2. clk Input 1 Clock to read buffer.
3. Cmd_en Input 1 This is command enable to read buffer from host.
4. flush_in Input 1 To reset the address after operation.
5. full_in Input 1 This is signal from FSM of master to read buffer for stopping
further reading.
6. temp_in Input 1 This is for reading data from read buffer.

7. d_out Output 8 output data from write buffer.
8. full_rd_buff Output 1 It high when read buffer is full.
9. empty_rd_buff Output 1 It high when read buffer is empty.

RTL DESIGN OF FSM WITHOUT BUFFER

PIN FUNCTION OF MASTER FSM
NO. NAME OF PINS DIRECT NO. FUNCTION
ION OF
PINS
1. I2c_master_data_in input 8 Input data to master FSM.
2. i2c_master_slave_addr Input 7 Input address of slave to master FSM.
_in
3. i2c_master_clock_in Input 1 Clock to master FSM.
4. i2c_master_reset_in Input 1 To reset the master FSM after operation.
5. i2c_master_start_in Input 1 To start the master FSM for following operation:
1. master to slave communication.
2. slave to master communication.
6. i2c_master_write_in Input 1 This is read and write bit to master FSM.

ION OF
PINS
1. byte_counter output 2 It count the number of bytes send/receive by master FSM.
2. count_bit_value output 3 It count the number of bit send/receive by master FSM.
3. c_state Output 4 It shows the current state of master FSM
4. n_state Output 4 It shows the next state of master FSM
5. i2c_master_data_out Output 8 Output data from master FSM.
6. count_bit_done output 1 This is enable when master FSM send 8 bit data to SDA line.

ION OF
PINS
1. i2c_master_busy_out output 1 It enable when master FSM performing operation.
2. i2c_transmit_done_out output 1 It enable when master FSM done following operation:

3. i2c_recieve_valid_out Output 1 It enable when master FSM receive 4 Bytes of data from
slave.
4. i2c_master_sda_io Inout 1 It is bidirectional data line where data can be transmitted to
slave.
5. i2c_master_scl_io Inout 1 It is bidirectional clock line.

RTL VERIFICATION OF WRITE FSM WITHOUT BUFFER
Signal Operation
reset_in=1 Master FSM in idle state.
reset_in=0, start_in=1,write_in=0 Master to slave communication
reset_in=0, start_in=1,write_in=1 Slave to master communication
reset_in=0, start_in=0,write_in=X Master FSM in idle state.

RTL VERIFICATION OF WRITE FSM WITHOUT BUFFER

RTL VERIFICATION OF READ MASTER FSM WITHOUT BUFFER
Signal Operation
reset_in=1 Master FSM in idle state.
reset_in=0, start_in=1,write_in=0 Master to slave communication
reset_in=0, start_in=1,write_in=1 Slave to master communication
reset_in=0, start_in=0,write_in=X Master FSM in idle state.

RTL VERIFICATION OF READ FSM WITHOUT BUFFER

TOP LEVEL RTL DESIGN OF MASTER

PIN FUNCTION OF TOP LEVEL MASTER
ION OF
PINS
1. I2c_master_data_in input 8 Input data to master.
2. i2c_master_slave_addr Input 7 Input address of slave to master.
_in
3. i2c_master_clock_in Input 1 Clock to master.
4. i2c_master_reset_in Input 1 To reset the master after operation.
5. Cmd_in Input 1 It is command from host to master for performing following
operation:
6. i2c_master_write_in Input 1 This is read and write bit to master.

ION OF
PINS
1. byte_counter output 2 It count the number of bytes send/receive by master.
2. count_bit_value output 3 It count the number of bit send/receive by master.
3. c_state Output 4 It shows the current state of master.
4. n_state Output 4 It shows the next state of master.
5. i2c_master_data_out Output 8 Output data from master.
6. count_bit_done output 1 This is enable when master send 8 bit data to SDA line.

ION OF
PINS
1. Cmd_en input 1 It enable for command to master.
2. i2c_transmit_done_out output 1 It enable when master FSM done following operation:

3. i2c_master_sda_io Inout 1 It is bidirectional data line where data can be transmitted to
slave.
4. i2c_master_scl_io Inout 1 It is bidirectional clock line.

Signal Operation
TOP LEVEL RTL reset_in=1 SDA=1 ,SCL=1

VERIFICATION
WRITE OF reset_in=0, full write buffer=1,write_in=0 Master to slave communication
MASTER
reset_in=0, write_in=1, slave to master communication
empty read buffer=1.

TOP LEVEL RTL VERIFICATION WRITE OF MASTER

Signal Operation
reset_in=1 SDA=1 ,SCL=1
TOP LEVEL RTL reset_in=0, full write buffer=1,write_in=0 Master to slave communication
VERIFICATION
READ OF reset_in=0, write_in=1, slave to master communication
MASTER empty read buffer=1.

TOP LEVEL RTL VERIFICATION READ OF MASTER

All electronics that uses a core
microcontroller or processor.
Enables designers to add feature to

existing design.
USES AND
APPLICATION Especially useful for Mobile and Laptop
where weight and space consideration.
A communication between multiple

master and multiple slave

Designs proceed rapidly from block diagram to final
schematic.
Integrated addressing and data-transfer protocol

allow systems to be completely software-defined.
DESIGNER
BENEFITS OF Design-time reduces.
I2C BUS
Fault diagnosis and debugging are simple.
Software development time can be reduced by

assembling a library of reusable software modules.

Simple 2-wire serial I2C-bus minimizes
interconnections, so ICs have fewer pins.
Eliminates the need for address decoders.
MANUFACTURER
BENEFITS OF I2C Increase system design flexibility and making simple
construction.
BUS
Easy upgrading to keep designs up-to-date.
It is easy to add new features to equipment or to

increase its performance.

Simple Hardware standard.
Easy to add / remove functions or devices (hardware

and software).
Easy to upgrade applications.

I2C Advantages
Simpler PCB: Only 2 traces required to communicate
between devices.
Very convenient for monitoring applications.
Well known and robust bus.

The bus capacitance limits the
number of interfaces connected to
the bus.
I2C An internal interrupted slave can

hold the clock line SCL LOW and
LIMITATION force the master into a wait state.
I²C supports a limited range of

speeds

The literature survey that we have done from that we able
to abstract specification for I2C bus implementation.
Master block :Read and write unit , Data frame generator ,

Shift register , Memory, clock synchronizer , etc.
CONCLUSION Slave block :Address memory , Read and write unit , Ack
and Nack generator , Shift register, clock synchronizer , etc.
The internal block of master and slave are abstracted.
Top level diagram is design.

REFERENCES
• G. UM10204, I2C-bus specification and user manual Rev. 6 — 4 Apr.2014,
[online] Available : http://www.nxp.com.
• Sangepu Dhivya “IMPLEMENTATION OF I2C SINGLE MASTER MULTIPLE SLAVE BUS
CONTROLLER ON FPGA,” International Journal on Electronics & Communication (IIJEC), India,
Jan. 1-21, 2014 .
• Bollam Eswari, N.Ponmagal, K.Preethi, S.G.Sreejeesh, “Implementation of I2C Master Bus
Controller on FPGA,” International conference on Communication and Signal Processing,
India, Apr. 3-5, 2013.
• I2C by Umang gajera.

THANK YOU

I2C Protocol Implementation: Guided By: MR .Y.V. Joshi Mr. Vaibbhav Taraate

Загружено:

Сведения о документе

Исходное описание:

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

I2C Protocol Implementation: Guided By: MR .Y.V. Joshi Mr. Vaibbhav Taraate

Загружено:

Авторское право:

Доступные форматы

I2C PROTOCOL

29-07-2019 I2C BUS IMPLEMENTATION 2

Invented by Philips (NXP) in 1982.

It is also known as TWI(Two Wire Interface)

29-7-2019 I2C BUS IMPLEMENTATION 6

Each device connected to the bus is software

If multi-master initiate data transfer, then collision

29-07-2019 I2C BUS IMPLEMENTATION To be continued…. 4

I2C-BUS On-chip filtering rejects spikes

The number of ICs that can be

PINS AND 1.Serial Data Line (SDA):

2.Serial Clock Line (SCL):

29-07-2019 I2C BUS IMPLEMENTATION 7

Element that addressed by master.

A slave cannot initiate a transfer over

29-07-2019 I2C BUS IMPLEMENTATION 8

Data, Select and R/W signals can share the

An asynchronous communication does not have

A point to point communication does not

29-07-2019 I2C BUS IMPLEMENTATION 10

29-07-2019 I2C BUS IMPLEMENTATION 11

Slave acknowledges it by sending back an Acknowledge (ACK) bit to the

When Master wants to stop writing it then sends a STOP condition.

29-07-2019 I2C BUS IMPLEMENTATION 12

Slave acknowledges it by sending back an Acknowledge (ACK) bit to the

Next, the Slave sends 1 or more bytes

Then master send STOP condition.

29-07-2019 I2C BUS IMPLEMENTATION 13

• A HIGH to LOW transition on

29-07-2019 I2C BUS IMPLEMENTATION 14

• The data on the SDA line

29-07-2019 I2C BUS IMPLEMENTATION 15

29-07-2019 I2C BUS IMPLEMENTATION 16

29-07-2019 I2C BUS IMPLEMENTATION 17

OF TOP- SCL(Serial Clock line) Bidirectional - The line on which clock is

reset_n Unidirectional 1 bit It is asynchronous active low reset.

clk Unidirectional 1 bit It is clock input to master.

29-07-2019 I2C BUS IMPLEMENTATION 23

1. d_in input 8 Input data to write buffer.

6. temp_in Input 1 This is for reading data from write buffer.

reset_n=0,full_in=1, No more write operation can be done

29-07-2019 I2C BUS IMPLEMENTATION 25

29-07-2019 I2C BUS IMPLEMENTATION 26

29-07-2019 I2C BUS IMPLEMENTATION 27

1. d_in input 8 Input data to read buffer.

6. temp_in Input 1 This is for reading data from read buffer.

29-07-2019 I2C BUS IMPLEMENTATION 28

29-07-2019 I2C BUS IMPLEMENTATION 29

29-07-2019 I2C BUS IMPLEMENTATION 30

1. byte_counter output 2 It count the number of bytes send/receive by master FSM.

2. count_bit_value output 3 It count the number of bit send/receive by master FSM.

3. c_state Output 4 It shows the current state of master FSM

4. n_state Output 4 It shows the next state of master FSM

5. i2c_master_data_out Output 8 Output data from master FSM.

29-07-2019 I2C BUS IMPLEMENTATION 31

1. i2c_master_busy_out output 1 It enable when master FSM performing operation.

2. i2c_transmit_done_out output 1 It enable when master FSM done following operation:

29-07-2019 I2C BUS IMPLEMENTATION 32

reset_in=0, start_in=0,write_in=X Master FSM in idle state.

29-07-2019 I2C BUS IMPLEMENTATION 33

29-07-2019 I2C BUS IMPLEMENTATION 34

29-07-2019 I2C BUS IMPLEMENTATION 35