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Chapter 7
Input/Output
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Input/Output
 The computer system’s I/O architecture is its interface to the outside
world. This architecture is designed to provide a systematic means of
controlling interaction with the outside world and to provide the
operating system with the information it needs to manage I/O activity
effectively.

 Three techniques are possible for I/O operations:


 Programmed I/O
 Data are exchanged between the processor and the I/O module
 Processor executes a program that gives it direct control of the I/O
operation
 When the processor issues a command it must wait until the I/O operation is
complete
 If the processor is faster than the I/O module this is wasteful of processor
time
 Interrupt-driven I/O
 Processor issues an I/O command, continues to execute other instructions,
and is interrupted by the I/O module when the latter has completed its work
 Direct memory access (DMA)
 The I/O module and main memory exchange data directly without
processor involvement
+ Why one does not connect peripherals directly to the
system bus. The reasons are as follows:
■There are a wide variety of peripherals with various methods of
operation. It would be impractical for the processor to accommodate all.

■The data transfer rate of peripherals is often much slower than that of the
memory or processor. Thus, it is impractical to use the high-speed system
bus to communicate directly with a peripheral.

■The data transfer rate of some peripherals is faster than that of the
memory or processor. Again, the mismatch would lead to inefficiencies if
not managed properly.

■ Peripheral often use different data formats and word lengths.

 Thus, an I/O module is required. This module has two major


functions:
■ Interface to the processor and memory via the system bus or central
switch.

■ Interface to one or more peripheral devices.


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Generic
Model
of an I/O
Module
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External Devices

 Three categories:
 Provide a means of
exchanging data between the  Human readable
external environment and the  Suitable for communicating with
computer the computer user
 Video display terminals (VDTs),
printers
 Attach to the computer by a
link to an I/O module  Machine readable
 The link is used to exchange  Suitable for communicating with
control, status, and data equipment
between the I/O module and  Magnetic disk and tape systems,
the external device sensors and actuators

 Communication
 peripheral device
 Suitable for communicating with
 An external device connected remote devices such as a terminal,
to an I/O module a machine readable device, or
another computer
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External
Device
Block
Diagram
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The External Device – I/O Module

 Control signals - determine the function that will be


performed

 Data - set of bits to be sent of received

 Status signals - indicate the state of the device

 Control logic - controls the device’s operations

 Transducer - converts data from electrical to other forms of


energy

 Buffer - temporarily holds data being transferred


Most common means of
+ computer/user interaction
Keyboard/Monitor User provides input through the
keyboard
The monitor displays data
International Reference provided by the computer
Alphabet (IRA)

 Basic unit of exchange is the character Keyboard Codes


 Associated with each character is a code
 Each character in this code is  When the user depresses a key it
represented by a unique 7-bit binary generates an electronic signal that is
code interpreted by the transducer in the
 128 different characters can be keyboard and translated into the bit
represented pattern of the corresponding IRA code

 Characters are of two types:  This bit pattern is transmitted to the I/O
 Printable module in the computer
 Alphabetic, numeric, and special
characters that can be printed on  On output, IRA code characters are
paper or displayed on a screen transmitted to an external device from the
 Control I/O module
 Have to do with controlling the
printing or displaying of characters  The transducer interprets the code and
 Example is carriage return
sends the required electronic signals to
the output device either to display the
 Other control characters are
concerned with communications indicated character or perform the
procedures requested control function
I/O Modules Control and
timing
•Coordinates the

Module Function flow of traffic


between internal
resources and
external devices

Processor
communication
Error detection
•Involves command
•Detects and reports decoding, data,
transmission errors status reporting,
The major address
functions for recognition
an I/O module
fall into the
following
categories:

Data buffering Device


•Performs the communication
needed buffering •Involves
operation to commands, status
balance device and information, and
memory speeds data
I/O Module Structure
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Programmed I/O

Overview of Programmed I/O


 Processor executes an I/O instruction by issuing command to
appropriate I/O module

 I/O module performs the requested action and then sets the
appropriate bits in the I/O status register – I/O module takes
not further action to alert the processor – it does not interrupt
the processor

 The processor periodically checks the status of the I/O


module until it determines that the operation is complete
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I/O Commands
 There are four types of I/O commands that an I/O module may
receive when it is addressed by a processor:

1) Control
- used to activate a peripheral and tell it what to do

2) Test
- used to test various status conditions associated with an I/O
module and its peripherals

3) Read
- causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer

4) Write
- causes the I/O module to take an item of data from the data bus
and subsequently transmit that data item to the peripheral
Three
Techniques
for Input of a
Block of Data
I/O Instructions
With programmed I/O there is a close correspondence between the I/O-related
instructions that the processor fetches from memory and the I/O commands that
the processor issues to an I/O module to execute the instructions

Each I/O device connected through I/O modules is given a


unique identifier or address

The form of the


When the processor
issues an I/O Memory-mapped I/O
instruction depends command, the
on the way in which command contains the
external devices are address of the desired
addressed device

Thus each I/O module There is a single address space for A single read line and a single write
must interpret the memory locations and I/O devices line are needed on the bus
address lines to
determine if the
command is for itself
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I/O Mapping Summary

 Memory mapped I/O


 Devices and memory share an address space
 I/O looks just like memory read/write
 No special commands for I/O
 Large selection of memory access commands available

 Isolated I/O
 Separate address spaces
 Need I/O or memory select lines
 Special commands for I/O
 Limited set
Memory
Mapped
I/O

Isolated
I/O

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Interrupt-Driven I/O
The problem with programmed I/O is that the
processor has to wait a long time for the I/O module
to be ready for either reception or transmission of
data

An alternative is for the processor to issue an I/O


command to a module and then go on to do some
other useful work

The I/O module will then interrupt the processor to


request service when it is ready to exchange data
with the processor

The processor executes the data transfer and


resumes its former processing
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Simple Interrupt
Processing
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Changes
in Memory
and Registers
for an
Interrupt
Design Issues

• Because there will


be multiple I/O
modules how does
the processor
determine which
Two design device issued the
interrupt?
issues arise in
implementing • If multiple
interrupt I/O: interrupts have
occurred how
does the
processor decide
which one to
process?
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Device Identification
Four general categories of techniques are in
common use:
 Multiple interrupt lines
 Between the processor and the I/O modules
 Most straightforward approach to the problem
 Consequently even if multiple lines are used, it is likely that each line will have multiple I/O modules
attached to it

 Software poll
 When processor detects an interrupt it branches to an interrupt-service routine whose job is to poll
each I/O module to determine which module caused the interrupt
 Time consuming

 Daisy chain (hardware poll, vectored)


 The interrupt acknowledge line is daisy chained through the modules
 Vector – address of the I/O module or some other unique identifier
 Vectored interrupt – processor uses the vector as a pointer to the appropriate device-service routine,
avoiding the need to execute a general interrupt-service routine first

 Bus arbitration (vectored)


 An I/O module must first gain control of the bus before it can raise the interrupt request line
 When the processor detects the interrupt it responds on the interrupt acknowledge line
 Then the requesting module places its vector on the data lines
Drawbacks of Programmed and
Interrupt-Driven I/O

 Both forms of I/O suffer from two inherent


drawbacks:

1) The I/O transfer rate is limited by the speed


with which the processor can test and service
a device

2) The processor is tied up in managing an I/O


transfer; a number of instructions must be
executed for each I/O transfer

 When large volumes of data are to be moved, a more


efficient technique is direct memory access (DMA)
Direct Memory Access

DMA Function

 DMA module on system bus used to mimic the


processor.

 DMA module only uses system bus when


processor does not need it.

+ DMA module may temporarily force processor


to suspend operations – cycle stealing.
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Typical DMA
Module Diagram
DMA

DMA

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DMA Operation
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Alternative
DMA
Configurations
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Evolution of the I/O Function

1. The CPU directly controls a


4. The I/O module is given direct
peripheral device. access to memory via DMA. It can
now move a block of data to or
2. A controller or I/O module from memory without involving
is added. The CPU uses the CPU, except at the beginning
programmed I/O without and end of the transfer.
interrupts.
5. The I/O module is enhanced to
become a processor in its own
3. Same configuration as in right, with a specialized
step 2 is used, but now instruction set tailored for I/O
interrupts are employed.
The CPU need not spend 6. The I/O module has a local
time waiting for an I/O memory of its own and is, in fact, a
operation to be performed, computer in its own right. With
thus increasing efficiency. this architecture a large set of I/O
devices can be controlled with
minimal CPU involvement.
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I/O
Channel
Architecture
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Parallel
and
Serial
I/O
Point-to-Point and Multipoint
Configurations

Multipoint external interfaces


Connection between an I/O Point-to-point interface are used to support external
module in a computer system provides a dedicated line mass storage devices (disk
and external devices can be between the I/O module and and tape drives) and
either: the external device multimedia devices (CD-
ROMs, video, audio)

On small systems (PCs,


workstations) typical
point-to-point links Are in effect external
point-to-point
include those to the buses
keyboard, printer, and
external modem

Example is EIA-232
multiport
specification
+ Universal Serial Bus (USB)

 USB is widely used for peripheral


connections. It is the default
interface for slower- speed  The first version, USB 1.0, defined a Low
devices, such as keyboard and Speed data rate of 1.5 Mbps and a Full
pointing devices, but is also Speed rate of 12 Mbps.
commonly used for high- speed
I/O, including printers, disk drives,  USB 2.0 provides a data rate of 480 Mbps.
and network adapters.
 USB 3.0 includes a new, higher speed bus
 A USB system is controlled by a called SuperSpeed in parallel with the USB
root host controller, which attaches 2.0 bus. The signaling speed of
to devices to create a local SuperSpeed is 5 Gbps, but due to signaling
network with a hierarchical tree overhead, the usable data rate is up to 4
topology. Gbps.

 The most recent specification is USB 3.1,


which includes a faster transfer mode
called SuperSpeed+. This transfer mode
achieves a signaling rate of 10 Gbps and a
theoretical usable data rate of 9.7 Gbps.
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Thunderbolt

 Provides up to 10 Gbps throughput


 Most recent and fastest in each direction and up to 10 Watts
of power to connected peripherals
peripheral connection
technology to become  A Thunderbolt-compatible
available for general-purpose peripheral interface is considerably
use more complex than a simple USB
device
 Developed by Intel with
collaboration from Apple
 First generation products are
 The technology combines primarily aimed at the professional-
consumer market such as
data, video, audio, and power audiovisual editors who want to be
into a single high-speed able to move large volumes of data
connection for peripherals quickly between storage devices
such as hard drives, RAID and laptops
arrays, video-capture boxes,
and network interfaces  Thunderbolt is a standard feature of
Apple’s MacBook Pro laptop and
iMac desktop computers
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Computer Configuration with Thunderbolt


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Thunderbolt
Protocol
Layers
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InfiniBand

 Recent I/O specification aimed at the high-end server market

 First version was released in early 2001

 Standard describes an architecture and specifications for


data flow among processors and intelligent I/O devices

 Has become a popular interface for storage area networking


and other large storage configurations

 Enables servers, remote storage, and other network devices


to be attached in a central fabric of switches and links

 The switch-based architecture can connect up to 64,000


servers, storage systems, and networking devices
InfiniBand Switch Fabric
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InfiniBand Operation

 Each physical link between a  The InfiniBand switch maps


switch and an attached traffic from an incoming lane
interface can support up to 16 to an outgoing lane to route
logical channels, called virtual the data between the desired
lanes
end points
 One lane is reserved for
fabric management and the
other lanes for data  A layered protocol
transport architecture is used, consisting
of four layers:
 A virtual lane is temporarily
 Physical
dedicated to the transfer of
data from one end node to  Link
another over the InfiniBand  Network
fabric
 Transport
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Table 7.3
InfiniBand Links and Data
Throughput Rates
InfiniBand Communication Protocol Stack