JC BOSE UNIVERSITY OF

SCIENCE AND TECNOLOGY

Presentation on
4 -Bit Shift Register
submitted by- Anju (18001752006)
Pooja (18001752035)
shilpa(18001752054)
simran(18001752056)
 TYPES OF DIGITAL
CIRCUITS
✓ COMBINATIONAL CIRCUITS –
- Present state o/p depends on present i/p.
- For eg : Adder, Multiplexer etc

✓ SEQUENTIAL CIRCUITS –
- Present state o/p depends on present i/p , as well as past 0/p.
- For eg : Flip flops, counters etc.
 BLOCK DIAGRAM OF
SEQUENTIAL CIRCUITS
 LATCHES
Latch is a device with exactly two stable states ,
i.e. example of Bistable Multivibrator.
It is of two types:
❑ SR LATCH USING NOR GATE
❑ SR LATCH USING NAND GATE
 CLOCK PULSE
● A Clock pulse is a time varying voltage signal applied to control the
operation (triggering) of a flip flop.

● Duty cycle – It is the ratio of time signal at which it is high to the total time.
 TRIGGERING

● The output of a flip flop can be changed by bring a small change in the
input signal. This small change can be brought with the help of a clock
pulse or commonly known as a trigger pulse.
● It is of two types :
✓ LEVEL TRIGGERING
✓ EDGE TRIGGERING –
• Positive ( +)
• Negative ( -)
 Flip-Flop
● They have 1 (HIGH) or 0 (LOW)
● More complicated Flip Flop use a clock as the
control input. These clocked flips flops are used
whenever the input and output signals must
occur within a particular sequence.
 Flip-flops have two outputs which are usually labeled P
and Q that are always compliment of each other i.e. P= 1
when Q = 0.
INPUTS INPUTS
P=1 P=0

Q=0 Q=1

SET STATE RESET STATE

The stable states of a flip-flop
Flip-flops can settle in any one of two stable states and are often referred
to as bistable circuits. The two stable states are illustrated in Fig 2.
Note that:
• in the SET state, P = 1 and Q = 0.
• in the RESET state, P = 0 and Q = 1.
Types of Flip-Flops
SR
Flip-
DFlop
Flip
Flop
(“set-
(“data”
reset”)
T
or
Flip-
“delay
Flop
”)
JK
(“toggl
Flip-
e”)
Flop
(“univ
ersal”)
 SR FLIP-FLOP
• Here SR stand for set reset
• These basic flip flop circuit can be constructed using
NAND gates or NOR gates .
UNCLOCKED SR flip flop using
NAND and NOR GATE
CLOCKED SR FLIP-FLOP USING
NAND AND NOR GATE
 D FLIP-FLOP
• Can be constructed from RS
flip flop or JK flip flop by
addition of an inverter
• Inverter is connected so that
the R input is always the
inverse of S(or J input is
always complements of K )
• The D flip flop will act as a
storage element for a
single binarydigit(Bit)
D FLIP-FLOP
 JK FLIP-FLOP
● It differs from the SR flip flop when J=K=1
condition is indeterminate but it is defined to
give a very useful changeover (toggle) action
● Toggle means that Q and Q will switch to their
opposite states
● The JK flip flop has clock input and two control
input J and K
 Symbol and circuit diagram

• Operation of JK flip flop is completely described

by truth table in figure
➢The difference this time is that the “JK
flip flop” has no invalid or forbidden
input states of the SR Latch even when S
and R are both at logic “1”.

➢A JK flip-flop has four

possible input
combinations, “logic 1”,
“logic 0”, “no change”
and “toggle”.
DESCRIPTION

The Truth Table for the JK Function

Input Output
Description
J K Q Q

0 0 0 0 Memory
same as no change
0 0 0 1
for the
0 1 1 0
SR Latch Reset Q » 0
0 1 0 1

1 0 0 1
Set Q » 1
1 0 1 0

1 1 0 1
toggle
Toggle
action 1 1 1 0
 T FLIP-FLOP
The T or
"toggle" flip-flop
changes its output
on each clock edge,
giving an output
which is half the
frequency of the
signal to the T input.
SHIFT REGISTERS
A register is a digital circuit with two basic functions :
DATA STORAGE and DATA MOVEMENT
● A shift register provide the data movement function
● A shift register “shifts” its output once every clock
cycle

A shift register is a group of flip flops set up

in a linear fashion with their inputs and
outputs connected together in such a way
that the data is shifted from one device to
another when the circuit is active
 SHIFT REGISTERS
➢The simplest shift register is one that uses only Flip-Flops
➢The output of a given Flip-Flop is connected to the D input
of the Flip-Flop at its right.
➢Each clock pulse shifts the contents of the register one bit
position to the right.
➢The Serial input(SI) determines what goes into the leftmost
Flip-Flop during the shift. The Serial output(SO) is taken
from the output of the rightmost Flip-Flop.
 Shift register characteristics

● Types
✓ serial-in , serial-out
✓ Serial-in , parallel-out
✓ Serial –in , parallel out
✓ Parallel-in , parallel-out
●Direction
✓ Left shift
✓ Right shift
✓ Rotate (right or left)
 DATA MOVEMENT

➢ The bits in a shift register can move in any of the

following manners
 Serial-In Serial-Out
➢Data bits come in one at a
time and leave one at a
time.
➢One Flip-Flop for each bit
to be handled.
➢Movement can be left or
right, but is usually only in
a single direction in a
given register.
➢Asynchronous preset
and clear inputs are
 Serial-In Serial-Out

➢A simple way of looking at

the serial shifting
operation, with a focus on
the data bits,is illustrated
at right
➢The 4-bit data word “1011”
is to be shifted into a 4-bit
shift register
➢One shift per clock pulse
➢Data is shown entering at
left and shifting right
2.) SERIAL IN-PARALLEL OUT
➢We often need to
convert from serial to
parallel
-e.g., after receiving a
series transmission
➢ The diagrams at the
right illustrate a 4-bit
serial-in parallel-out
shift register
 SERIAL IN-PARALLEL OUT
➢We would use a serial-in
parallel-out shift register of
arbitrary length N to convert an
N-bit word from serial to
parallel.
➢It would require N clock pulses
to LOAD and one clock pulse to
UNLOAD.
 3.)Parallel In-Serial Out
➢ We use a parallel-in serial-out shift
Register
➢ The DATA is applied in parallel from
to the parallel input pins PA to PD of
the register.
➢ It is then read out sequentially from
the register one bit at a time from PA
to PD on each clock cycle in a serial
format.
➢ One clock pulse to load
➢ Four pulses to unload
 4.)Parallel-In Parallel-Out
➢Parallel-in Parallel-out
shift Registers can
serves as a temporary
storage device or as a
time delay device.
➢The DATA is presented
in a parallel format to
the parallel input pins
PA to PD and then
shifted to the
corresponding output
pins QA to QD when the
registers are clocked
➢One clock pulse to load
➢One pulse to unload
THANK YOU