Building A CPU

• We’ve built a small ALU

• Add, Subtract, SLT, And, Or
• Could figure out Multiply and Divide...
• What about the rest
• How do we deal with memory and registers?
• What about control operations (branches)?
• How do we interpret instructions?
• The whole thing...
• A CPU’s datapath deals with moving data around
• A CPU’s control manages the data

5.1
 ALU Computes on:
Datapath Overview R-type: 2 registers
I-type: Register and data
Current Instruction: PC

Read reg. num A Read address

Read reg data A
Read address Read reg. num B Data Memory
PC Read data
Instruction [31-0] Registers Result Write address
Write reg num
Instruction Read reg dataB
Write data
Memory Write reg data

Instructions: Memory:
Data to write into
R-type: 3 registers Address from ALU
dest. register from:
I-type: 2 registers, Data Data to/from regs
ALU or Memory

5.1
Instruction Datapath
• Instructions will be held in
4 the instruction memory
• The instruction to fetch is at
Add
the location specified by the
PC
• Instr. = M[PC]
PC Read address
Instruction • After we fetch one
Instruction instruction, the PC must be
Memory
incremented to the next
instruction
• All instructions are 4 bytes
Note: Regular instruction width • PC = PC + 4
(32 for MIPS) makes this easy

5.2
 R-type Instruction Datapath
Read reg. num AA
reg num
Read reg data A
Instruction Read reg num B
Zero
Registers Result
Write reg num
Read reg data B ALU
Write reg data

• R-type Instructions have three registers

• Two read (Rs, Rt) to provide data to the ALU
• One write (Rd) to receive data from the ALU
• We’ll need to specify the operation to the ALU (later...)
• We might be interested if the result of the ALU is zero (later...)

5.2
 Memory Operations
Read reg. num AA
reg num Read address
Read reg data A
Instruction Read reg num B Data Memory
Zero Read data
Registers
Result Write address
Write reg num
Read reg data B
Write data
Write reg data

16 sign 32
extend

• Memory operations first need to compute the effective address

• LW $t1, 450($s3) # E.A. = 450 + $s3
• Add together one register and 16 bits of immediate data
• Immediate data needs to be converted from 16-bit to 32-bit
• Memory then performs load or store using destination register

5.2
 Branches
PC + 4 • Branches conditionally
change the next instruction
Result

Instruction Sh. Add • BEQ $2, $1, 42

Left
2 • The offset is specified as
To control the number of words to be
Read reg. num AA
reg num
Read reg data A
Read reg num B
logic added to the next
Registers
Zero
Result
instruction (PC+4)
Write reg num
Read reg data B • Take offset, multiply by 4
• Shift left two
Write reg data

offset 16 32
• Add this to PC+4 (from PC
sign
extend logic)

• Control logic has to decide if

the branch is taken
• Uses ‘zero’ output of ALU

5.2
 Integrating the R-types and Memory
Read reg. num AA
reg num Read address
Read reg data A
Instruction Read reg num B Data Memory
Zero Read data 1
Registers
Result Write address
Write reg num 0
Read reg data B 0
Write data
Write reg data
Memory 1

Datapath
16 sign 32
extend

• R-types and Load/Stores are similar in many respects

• Differences:
• 2nd ALU source: R-types use register, I-types use Immediate
• Write Data: R-types use ALU result, I-types use memory
• Mux the conflicting datapaths together

5.3
 Adding the instruction memory
4 Simply add the instruction memory
Result and PC to the beginning of the datapath.
Add

Read reg. num AA

reg num Read address
Read reg data A
Read address Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
Write reg num
Instruction Read reg data B 0 0
Write data
Memory Write reg data 1

16 sign 32
extend

Separate Instruction and Data memories are needed in order to allow

the entire datapath to complete its job in a single clock cycle.

5.3
 Adding the Branch Datapath
0
4
Result 1
Result
Sh. Add
Add Left
2

Read reg. num AA

reg num Read address
Read reg data A
Read address Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
Write reg num
Instruction Read reg data B 0 0
Write data
Memory Write reg data 1

16 sign 32
extend

Now we have the datapath for R-type, I-type, and branch instructions.
On to the control logic!

5.3
 When does everything happen?
0

4 Result 1
Result clk Sh. Add
Left
Add 2 Single-Cycle Design
Read reg. num AA
reg num Read address
Read reg data A
Read address
Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
Write reg num
Instruction Read reg data B 0 0
Write data
Memory Write reg data 1
clk
16 sign
extend
32
clk
Combinational Logic:
Just does it! Outputs are
always just a function of its Registers: Written at the end of the clock cycle.
inputs (with some delay) (Rising edge triggered).

5.3
 Example
• Suppose it takes:
• memory 100 nsec to read a word,
• the ALU and adders take 4 nsec,
• the register file can be read or written in 1 nsec,
• the PC can be read or written in 0.2 nsec,
• all multiplexors take 0.1 nsec.
• Assume everything else takes 0 time (control, shift,
sign extend, wires, etc.).
• How long will it take to execute an add instruction?
• How long will it take to execute a lw instruction?
• How long will it take to execute a beq instruction?
• How long will it take to execute a j instruction?
 What do we need to control? Mux - are we
branching or not?

Registers- 0

4 Should we
Result 1
write data? Mux - Result from
Result Sh. Add
Add
Left ALU or Memory?
2

Read reg. num AA

reg num Read address
Read reg data A
Read address
Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
Write reg num
Instruction Read reg data B 0 0
Write data
Memory Write reg data 1

16 sign 32
Mux - Where
extend Memory-
does 2nd ALU ALU - Read/Write/neither?
operand come What is the
from? Operation?

Almost all of the information we need is in the instruction!

5.3
 The ALU
• The ALU is stuck right in the middle of everything...
• It must:
• Add, Subtract, And, or Or for arithmetic instructions
• Subtract for a branch on equal
• Subtract and set for a SLT BInvert CarryIn Operation

• Add for a memory access A 0

Function BInvert Op Carryin Result 1

Result
And 0 00 0 R=A•B B 0
Or 0 01 0 R=AB 1
+ 2

Add 0 10 0 R=A+B Less 3

Subtract 1 10 1 R=A-B
SLT 1 11 1 R = 1 if A < B
CarryOut
0 if A B

Always the same: Combine into one signal called “sub”

5.3
 Setting the ALU controls
• The instruction Opcode and Function give us the info we need
• For R-type instructions, Opcode is zero, function code
determines ALU controls
• For I-type instructions, Opcode determines ALU controls
New control signal: ALUOp is 00 for memory, 01 for Branch, and 10 for R-type

Instruction Opcode ALUOp Funct. Code ALU action ALU control

sub op
add R-type 10 100000 add 0 10
sub R-type 10 100010 subtract 1 10
and R-type 10 100100 and 0 00
or R-type 10 100101 or 0 01
SLT R-type 10 101010 SLT 1 11
load word LW 00 xxxxxx add 0 10
store word SW 00 xxxxxx add 0 10
branch equal BEQ 01 xxxxxx subtract 1 10
5.3
 Controlling the ALU
AluOp is determined by Opcode - For ALUOp = 00 or 01,
separate logic will generate ALUOp function code is unused

ALUOp F5 F4 F3 F2 F1 F0 Function ALU Ctrl

00 x x x x x x Add 0 10 ALUOp1
F1 A2
x1 x x x x x x Sub 1 10
1x x x 0 0 0 0 Add 0 10
ALUOp0
1x x x 0 0 1 0 Sub 1 10 A1
F2
1x x x 0 1 0 0 And 0 00
1x x x 0 1 0 1 Or 0 01 F3 A0
1x x x 1 0 1 0 SLT 1 11 F0

Since ALUOp can only

be 00, 01, or 10, we A 6-input truth table -
don’t care what ALUOp2 use standard
is when ALUOP1 is 1 minimization techniques

5.3
 Decoding the Instruction - Data
The instruction holds the key to all of the data signals

R-type 31-26 25-21 20-16 15-11 10-6 5-0

Opcode RS RT RD ShAmt Function
To ctrl Read Read Write Not To ALU
logic reg. A reg. B reg. Used Control

Memory,
31-26 25-21 20-16 15-0
Branch
Opcode RS RT Immediate Data
To ctrl Read Write Memory address or Branch Offset
logic reg. A reg./
Read
reg. B
One problem - Write register number must come from two different places.

5.3
 We can decode the data simply
Instruction Decoding by dividing up the instruction bus

4 Opcode: [31-26]
Result 1
Result Sh. Add
Left
Add Op:[31-26]
Ctrl 2

Rs:[25-21] Read reg. num AA

reg num Read address
Rt:[20-16] Read reg numdata
Read reg A
Read address
B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
0
Write reg num
Instruction Read reg data B 0 0
Rd: 1 Write data
Memory Write reg data 1
[15-11]

Read Reg A: Rs Imm:

[15-0] 16 sign 32
Read Reg B: Rt extend

Write Reg: Either Rd or Rt

Immediate Data: [15-0]

5.3
 Control Signals
0

4 Result 1
Result Load,R-type Sh. Add BEQ and zero
Left PCSrc
Add Op:[31-26]
MemWrite Load
Ctrl RegWrite 2
Store
Rs:[25-21] ALUSrc MemToReg
Read reg. num AA
reg num Read address
Rt:[20-16] Read reg data A
Read reg num B Data Memory
PC Read address Memory Zero Read data 1
Instruction [31-0] Registers
0 Result Write address
Write reg num
Instruction Read reg data B 0 0
Rd: 1 Write data
Memory [15-11] Write reg data 1

RegDest
Imm:
R-type [15-0] 16 sign 32 00: Memory MemRead
ALU
extend
Ctrl 01: Branch Load
10: R-type
FC:[5-0] 6
ALUOp

ALU Control - A function of: ALUOp and the function code

5.3
 Inside the control oval
00:Mem
0:Reg 1:Mem 0:Rt 01:Branch
1:Imm 0:ALU 1:Rd
1:Branch 10:R-type
Reg ALU Mem Reg Mem Mem
Instruction Opcode Write Src To Reg Dest Read Write PCSrc ALUOp
R-format 000000 1 0 0 1 0 0 0 10
LW 100011 1 1 1 0 1 0 0 00
SW 101011 0 1 x x 0 1 0 00
BEQ 000100 0 0 x x 0 0 1 01

• This control logic can be decoded in several ways:

• Random logic, PLA, PAL
• Just build hardware that looks for the 4 opcodes
• For each opcode, assert the appropriate signals
Note: BEQ must also check the zero output of the ALU...

5.3
 We must AND
BEQ and Zero
Control Signals
0

4 Result 1
Result Sh. Add
Left PCSrc
Add 2
BEQ
MemToReg
MemRead
Op:[31-26] MemWrite
Ctrl ALUOp
ALUSrc
RegWrite
RegDest
Rs:[25-21] Write Read
Read reg. num AA
reg num Read address
Rt:[20-16] Read reg data A
Read address
Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
0
Write reg num
Instruction Read reg data B 0 0
Rd: 1 Write data
Memory [15-11] Write reg data 1

Imm:
[15-0] 16 32
sign
ALU
extend
Ctrl

FC:[5-0] 6

5.3
 Jumping 32
1

Sh. 28
26 0
Left
Concat. 0
4 2 4 Result 1
[31-28]
Result Sh. Add
Jump Left PCSrc
Add J:[25-0] 2
BEQ
MemToReg
MemRead
Op:[31-26] MemWrite
Ctrl ALUOp
ALUSrc
RegWrite
RegDest
Rs:[25-21] Write Read
Read reg. num AA
reg num Read address
Rt:[20-16] Read reg data A
Read address
Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
0
Write reg num
Instruction Read reg data B 0 0
Rd: 1 Write data
Memory [15-11] Write reg data 1

Imm:
[15-0] 16 32
sign
ALU
extend
Ctrl

FC:[5-0] 6

5.3
 Performance
What major functional units are used by different instructions?

R-type: Instr. Fetch Register Read ALU Register Write 6ns

LW: Instr. Fetch Register Read ALU Memory Read Register Write 8ns
SW: Instr. Fetch Register Read ALU Memory Write 7ns
Branch: Instr. Fetch Register Read ALU 5ns
Jump: Instr. Fetch 2ns

Assume the following times: Since the longest time is 8ns (LW),
Memory Access: 2ns the cycle time must be at least 8ns.
ALU: 2ns
Registers: 1ns
 Example
• Calculate the execution times for the following
program in a Single-cycle datapath with a cycle time
of 50 ns
main:
add $9, $0, $0 # clear $9
lw $8, Tonto($9) # put Tonto[0] in $8
addi $9, $9, 4 # increment $9
lw $10, Tonto($9) # put Tonto[1] in $10
add $11, $10, $8
 Example 2
Calculate the execution times for the following
program in a Single-cycle datapath with a cycle time
of 50 ns
.data
ARRAY: .word 3, 5, 7, 9, 2 #random values
SUM: .word 0 #initialize sum to zero
.text
main: addi $6, $0, 5 #initialize loop counter to 5
addi $7, $0, 0 #initialize array index to zero
addi $8, $0, 0 #set $8 (sum temp) to zero
REPEAT: lw $5, ARRAY($7) #R5 = ARRAY[i]
add $8, $8, $5 #SUM+= ARRAY[I]
addi $7, $7, 4 #increment index (i++)
addi $6, $6, -1 #decrement loop counter
bne $6, $0, REPEAT #check if 5 repetitions
sw $8, SUM($0) #copy sum to memory
addi $v0, $0, 10 #exit program
syscall