Unit Iii

Name of Subject :
Computer Organization and Architecture

Code:CS215A (Credits 2)
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Module 1: (7)
Computer Function, Interconnections and Evolution
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Module 2: (8)
Computer Arithmetic
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Module 3: (8)
Processor Organization and Control Unit
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Module 4: (7)
Memory and Parallel Processor Organizations
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Objectives & Outcomes
Unit Objectives :
1. To acquire the knowledge of structure, function and evolution of computer
systems.
2. To design Arithmetic Logical Unit and Control Unit of digital computers.
3. To understand instruction level parallelism and internal processor
organization.
4. To gain the conceptual knowledge of Cache memory and multiple processor
organization.
Unit Outcomes :
On completion of the course, student will be able to –
1. Demonstrate computer architecture concepts related to design of modern
processors and compare various generation of processors.
2. Design arithmetic functional units such as: Adder, Subtractor , Multiplier
and Division units.
3. Obtain the knowledge of processor structure and its functions for internal
designing of processor organization.
4. Design the size of the cache for the various processor organizations.
Contents
Module_3
Processor Organization and Control Unit
 Instruction format
 Types of Instruction and operations
Common addressing techniques
 Processor Structure and function - Processor and register
organization
 Instruction Cycle
Instruction Pipelining
 Pipeline Performance
Pipeline Hazards - Structural, Data, Control
Control Unit Operation - The functional requirement of processor
 Micro – operation and instruction cycle
 Functional Requirements & Operations of the Control Unit
Block diagram of control unit.

Objectives & Outcomes_ Module_3
Objective :
1. To understand instruction level Parallelism and internal
Processor Organization
Outcomes :
On completion of the course, student will be able to –
1. Obtain the knowledge of processor structure and its
functions for internal designing of processor Organization.

Instruction format
What is an Instruction Set?
• The complete collection of instructions that are
understood by a CPU
• Machine Code
• Binary
• Usually represented by assembly codes

Number of Addresses
• 1 address
– Implicit second address
– Usually a register (accumulator)
Instruction Comment
LOAD D AC ← D
STOR Y Y ← AC
• 0 (zero) addresses
– All addresses implicit
– Uses a stack
– e.g. push a
push b

Number of Addresses
Two key benefits of assembly language programming
– It takes up less memory
– It executes much faster
• 3 addresses
Operand 1, Operand 2, Result
a = b + c;
Instruction Comment
SUB Y,A,D Y←A–B
MPY T,D,E T ← D ×E
ADD T,T,C T←T+C
• 2 addresses
One address doubles as operand and result
a=a+b
Instruction Comment
MOV Y,A Y←A
SUB Y,B Y←Y–B
DIV Y,T Y ← Y ÷T

Converting Assembly Language Instructions to Machine Code
An instruction can be coded with 1 to 6 bytes

Byte 1 has three fields
– Opcode field (6 bits): specifies the operation (add, subtract, move)
---------------------------------------------------------------------------------------------
– Register Direction Bit (D bit): Tells the register operand in REG field in
byte 2 is source or destination operand
1: destination 0: source
--------------------------------------------------------------------------------------------
-Data Size Bit (W bit): Specifies whether the operation will be performed
on 8-bit or 16-bit data
0: 8 bits 1: 16 bits
-------------------------------------------------------------------------------------------
15 ------- 10 9 8 7 ---- 6 5 ---- 3 2 ---- 0

Converting Assembly Language Instructions to Machine Code cont-
Byte 2 has three fields

– Mode field (MOD)
– Register field (REG) used to identify the register for the first operand
– Register/memory field (R/M field)
MOD Explanation
00 Memory Mode, No Displacement
01 Memory Mode, 8-bit Displacement
11 Register Mode, No Displacement

• Byte 2 has three fields
– Mode field (MOD)
– Register field (REG) used to identify the register for the first operand
– Register/memory field (R/M field)
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MOD Explanation
Examples
00 Memory Mode, No Displacement
MOV BL,AL (88C316) 10 Memory Mode, 16-bit Displacement
Opcode for MOV = 100010 11 Register Mode, No Displacement
D = 0 (AL source operand)
W bit = 0 (8-bits)
Therefore byte 1 is
100010002=8816
• MOD = 11 (register mode)
• REG = 000 (code for AL)
• R/M = 011 (destination is BL)
Therefore Byte 2 is
110000112=C316
100010 0 0 11 000 011

Examples
MOV BL, AL = 10001000 11000011 = 88 C3h

ADD AX, [SI] = 00000011 00000100 = 03 04 h
ADD [BX] [DI] + 1234h, AX = 00000001 10000001 __ __ h =
01 81 34 12 h

Types of Operations
• Data Transfer
• Arithmetic
• Logical
• Conversion
• I/O
• System Control
• Transfer of Control

Data Transfer
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
MOV reg2/ mem, reg1/ mem (reg2)  (reg1)

MOV reg2, reg1 (mem)  (reg1)
MOV mem, reg1 (reg2)  (mem)
MOV reg2, mem
MOV reg/ mem, data (reg)  data
MOV reg, data (mem)  data
MOV mem, data
XCHG reg2/ mem, reg1 (reg2)  (reg1)

XCHG reg2, reg1 (mem)  (reg1)
XCHG mem, reg1
IN AL, [DX]
OUT [DX], AL
PUSH reg16
POP reg16

Arithmetic and Logical
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
----------------------------------------------------------------------------------
Logical
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
------------------------------------------------------------------------
String Manipulation Instructions
Mnemonics: REP, MOVS, MOVSB, MOVSW, CMPS, SCAS, LODS, STOS

Processor Control Instructions
Mnemonics Explanation
STC Set CF  1 ;set carry flag
CLC Clear CF  0
CMC Complement carry CF  CF/
STD Set direction flag DF  1
CLD Clear direction flag DF  0
STI Set interrupt enable flag IF  1
CLI Clear interrupt enable flag IF  0
NOP No operation
HLT Halt after interrupt is set
WAIT Wait for TEST pin active
LOCK Lock bus during next instruction

Control Transfer Instructions
 8086 Unconditional transfers  8086 signed conditional branch instructions
Mnemonics Explanation Name Alternate name
CALL reg/ mem/ Call subroutine JE disp8 JZ disp8

disp16 Jump if equal Jump if result is 0
RET Return from JNE disp8 JNZ disp8

subroutine Jump if not equal Jump if not zero
JMP reg/ mem/ Unconditional jump JG disp8 JNLE disp8
disp8/ disp16 Jump if greater Jump if not less or equal
JGE disp8 JNL disp8
Jump if greater than or Jump if not less
equal
JL disp8 JNGE disp8
Jump if less than Jump if not greater than
or equal
JLE disp8 JNG disp8
Jump if less than or Jump if not greater
equal

Conversion
Change the format or operate on the format of data

• E.g. Binary to Decimal
• CWD : Convert Word to Double word.
• ----------------------------------------------------------------------------------------
Input / Output
• May be done using data movement instructions
• IN and OUT

Addressing Modes
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack

Addressing Modes
1. Register Addressing
Group I : Addressing modes for register and immediate data
2. Immediate Addressing
-----------------------------------------------------------------------------------------
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing Group II : Addressing modes for memory data

6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
-----------------------------------------------------------------------------------------
9. Direct I/O port Addressing
10. Indirect I/O port Addressing

Group III : Addressing modes for I/O ports
-----------------------------------------------------------------------------------------
11. Relative Addressing
Group IV : Relative Addressing mode
------------------------------------------------------------------------------------------
12. Implied Addressing
Group V : Implied Addressing mode
Addressing Modes
Group I : Addressing modes for register and immediate data
1. Register Addressing
Example:
MOV CL, DH
2. Immediate Addressing
MOV DL, 08H
MOV AX, 0A9FH

Addressing Modes: Memory Access
Offset Value (16 bits)
Segment Register (16 bits) 0000
Adder
Physical Address (20 Bits)

To access memory we use these four registers: BX, SI, DI, BP
Combining these registers inside [ ] symbols, we can get different

memory locations (Effective Address, EA)
Supported combinations:
[BX + SI] [BX + SI + d8]

[SI]
[BX + DI] [BX + DI + d8]
[DI]
[BP + SI] [BP + SI + d8]
d16 (variable offset only)
[BP + DI] [BP + DI + d8]
[BX]
[SI + d8] [BX + SI + d16] [SI + d16]

[DI + d8] [BX + DI + d16] [DI + d16]
[BP + d8] [BP + SI + d16] [BP + d16]
[BX + d8] [BP + DI + d16] [BX + d16]
BX SI + disp
BP DI

Group II : Addressing modes for memory data

3. Direct Addressing
MOV BX, [1354H]
MOV BL, [0400H]
---------------------------------------
4. Register Indirect Addressing
MOV CX, [BX]
---------------------------------------
5. Based Addressing
MOV AX, [BX + 08H]
---------------------------------------
6. Indexed Addressing
MOV CX, [SI + 0A2H]
---------------------------------------
7. Based Index Addressing
MOV DX, [BX + SI + 0AH]
--------------------------------------

Direct Addressing Diagram
Instruction
Opcode Address A
Memory
Operand

Register Addressing
• Operand is held in register named in address filed
• EA = R
Register Address R
Registers
Operand

Register Indirect Addressing
• EA = (R)
• Operand is in memory cell pointed to by contents of register R
• Ex: LDR r0, [r1]

Register Indirect Addressing Diagram
Instruction
Opcode Register Address R
Memory
Registers
Pointer to Operand Operand

Displacement Addressing
• EA = A + (R)
• Address field hold two values
-A = base value
-R = register that holds displacement or vice versa

Displacement Addressing Diagram
Instruction
Opcode Register R Address A
Memory
Registers
Pointer to Operand Operand

9. Direct I/O port Addressing
IN AL, [09H]
11. Relative Addressing

JZ 0AH
12. Implied Addressing

CLC :This clears the carry flag to zero

Indexed Addressing
• A = base
• R = displacement
• EA = A + R

Processor Structure and Function
- Processor Organization
- Register Organization
- Instruction Cycle
Fetch Instruction
Interpret instruction
Fetch Data
Process Data
Write Data

CPU with System Bus

CPU Internal Structure

Register Organization
• User-visible registers
– General Purpose
– Data
– Address (Segment Registers, Index Pointers and Stack Pointers)
– Condition Codes (Flag Register)
• Control and status registers (Not Visible to user)
– Program Counter (PC)
– Instruction Decoding Register (IR)
– Memory Address Register (MAR)
– Memory Buffer Register (MBR)
– PSW (Program Status Word): Condition Codes + other status
information

Instruction Cycle
• It is the time in which a single instruction is fetched from
memory, decoded, and executed
• An Instruction Cycle requires the following sub cycle:

Fetch : Read next instruction from memory into the processor
Indirect Cycle (Decode Cycle):May require memory access to fetch

operands, therefore more memory accesses.
Interrupt : Save current instruction and service the interrupt
Execute: Interpret the opcode and perform the indicated operation

Indirect Cycle
• May require memory access to fetch operands
• Indirect addressing requires more memory accesses
• Can be thought of as additional instruction subcycle

Instruction Cycle
Fetch
Interrupt Indirect
Execute

Instruction Cycle State Diagram

What Is Pipelining
• Laundry Example
• Ann, Brian, Cathy, Dave A B C D
each have one load of clothes
to wash, dry, and fold wash
• Washer takes 30 minutes
dry
• Dryer takes 40 minutes
• “Folder” takes 20 minutes fold

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6 PM 7
What
8
Is Pipelining
9 10 11 Midnight
Time
30 40 20 30 40 20 30 40 20 30 40 20
T
a A
s
k wash, dry, and fold
B
O
wash, dry, and fold
r
C
d
e wash, dry, and fold
r D
wash, dry, and fold

Sequential laundry takes 6 hours for 4 loads
If they learned pipelining, how long would laundry take?
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What Is Pipelining
Start work ASAP
6 PM 7 8 9 10 11 Midnight
Time
30 40 40 40 40 20
T
a A
s wash, dry, and fold • Pipelined laundry takes 3.5
k hours for 4 loads
B
O
r
C
d
e
r D

Instruction Pipelining
• Instruction processing is subdivided:
- Fetch/ Execute instruction
• Pipeline has two independent stages:
1st Stage – Fetch an instruction and buffers it.
2nd Stage – Temporarily free until first stage passes it the
buffered instruction.
• While the second stage is executing the instruction, the first
stage fetches and buffers the next instruction.
• Instruction prefetch or fetch overlap.
- Purpose?  To speed up instruction execution.

Two-Stage Instruction Pipeline

Instruction Processing
• Fetch instruction (FI)

• Decode instruction (DI)
• Calculate operands (CO)
• Fetch operands (FO)
• Execute instruction (EI)
• Write operand (WO)
• Successive instructions in a program sequence will overlap in

execution.

Timing Diagram for Instruction Pipeline Operation
• Fetch instruction (FI)

• Decode instruction (DI)
• Calculate operands (CO)
• Fetch operands (FO)
• Execute instruction (EI)
• Write operand (WO)

Alternative Pipeline description

Pipeline Hazards
Resource Hazards
Two (or more) instructions in pipeline need same resource
Executed in serial rather than parallel for part of pipeline
Also called structural hazard

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Data Hazard Diagram
• Conflict in access of an operand location
• Two instructions to be executed in sequence
• Both access a particular memory or register operand
• If in strict sequence, no problem occurs

Types of Data Hazard
• Read after write (RAW), or true dependency
-An instruction modifies a register or memory location
-Succeeding instruction reads data in that location
-Hazard if read takes place before write complete
• Write after read (WAR), or antidependency
-An instruction reads a register or memory location
-Succeeding instruction writes to location
-Hazard if write completes before read takes place
• Write after write (WAW), or output dependency
-Two instructions both write to same location
-Hazard if writes take place in reverse of order intended
sequence.
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Control Hazard
• Also known as branch hazard

• Pipeline makes wrong decision on branch prediction
• Brings instructions into pipeline that must subsequently be
discarded
• Dealing with Branches
-Multiple Streams
-Prefetch Branch Target
-Loop buffer
-Branch prediction
-Delayed branching

Branch Prediction Flowchart& State Diagram

Control Unit Operation :Micro-Operations
• A computer executes a program

• Fetch/execute cycle
• Each cycle has a number of steps Called micro-operations
• Each step does very little operation
• Atomic operation of CPU

Micro Operations

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Definitions

Constituent Elements of
Program Execution

Instruction Cycle
• Each phase decomposed into sequence of elementary micro-
operations
• E.g. fetch, indirect, and interrupt cycles
• Execute cycle
-One sequence of micro-operations for each opcode
• Need to tie sequences together
• Assume new 2-bit register
-Instruction cycle code (ICC) designates which part of
cycle processor is in
00: Fetch
01: Indirect
10: Execute
11: Interrupt
Flowchart for Instruction Cycle
Instruction cycle code (ICC)
00: Fetch
01: Indirect
10: Execute
11: Interrupt

Functional Requirements
• Define basic elements of processor

• Describe micro-operations processor performs
• Determine functions control unit must perform
• Basic Elements of Processor
-ALU
-Registers
-Internal data paths
-External data paths
-Control Unit

Functions of Control Unit
• Sequencing
-Causing the CPU to step through a series of micro-
operations
• Execution
-Causing the performance of each micro-op
-This is done using Control Signals

Model of Control Unit

Control Unit Block Diagram

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Unit Iii

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Name of Subject :

Computer Organization and Architecture

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An instruction can be coded with 1 to 6 bytes

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Byte 2 has three fields

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100010 0 0 11 000 011

MOV BL, AL = 10001000 11000011 = 88 C3h

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MOV reg2/ mem, reg1/ mem (reg2)  (reg1)

XCHG reg2/ mem, reg1 (reg2)  (reg1)

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 8086 Unconditional transfers  8086 signed conditional branch instructions

Mnemonics Explanation Name Alternate name

CALL reg/ mem/ Call subroutine JE disp8 JZ disp8

RET Return from JNE disp8 JNZ disp8

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Change the format or operate on the format of data

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4. Register Indirect Addressing

5. Based Addressing Group II : Addressing modes for memory data

7. Based Index Addressing

10. Indirect I/O port Addressing

MOV DL, 08H

MOV AX, 0A9FH

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Offset Value (16 bits)

Segment Register (16 bits) 0000

Physical Address (20 Bits)

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Combining these registers inside [ ] symbols, we can get different

[BX + SI] [BX + SI + d8]

[SI + d8] [BX + SI + d16] [SI + d16]

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Group II : Addressing modes for memory data

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• Ex: LDR r0, [r1]

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Pointer to Operand Operand

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Pointer to Operand Operand

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11. Relative Addressing

12. Implied Addressing

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