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Combinational Circuits
Part 4
A = B, or EQ
4-bit input
A<B
B LE
Solution:
Inputs: 8-bits (A ⇒ 4-bits , B ⇒ 4-bits)
A and B are two 4-bit numbers 4-bit input 4-bit magnitude GT
Let A = A3A2A1A0 , and A comparator
Let B = B3B2B1B0 EQ
4-bit input
Inputs have 28 (256) possible
B
combinations (size of truth table LE
and K-map?)
Not easy to design using conventional
techniques
The circuit possesses certain amount of regularity
⇒ can be designed algorithmically.
Designing EQ:
GT = 1 if A > B:
• If A3 > B3 A3 = 1 and B3 = 0
• If A3 = B3 and A2 > B2
• If A3 = B3 and A2 = B2 and A1 > A1
• If A3 = B3 and A2 = B2 and A1 = B1 and A0 > B0
Therefore,
GT = A3B3‘ + X3 A2 B2‘ + X3 X2 A1 B1‘ + X3 X2 X1A0 B0‘
Similarly, LT = A3’B3 + X3 A2‘B2 + X3 X2 A1’B1 + X3 X2 X1A0’ B0
EQ = X3 X2 X1 X0
GT = A3B3’
+ X3A2B2’
+ X3X2A1B1’
+ X3X2X1A0B0’
LT = B3A3’
+ X3B2A2’
+ X3X2B1A1’
+ X3X2X1B0A0’
X3X2X1X0 S3S2S1S0
+ Y3Y2Y1Y0 + Z3Z2Z1Z0
------------------- -------------------
C4 S3S2S1S0 D4 F3F2F1F0
Note: C4 and D4 is generated in position 4. They must be
added to generate the most significant bits of the result
Solution: 0 1 0 0 D4
A3A2 = 01 0 1 0 1 D5
• Each group combination holds 0 1 1 0 D6
a unique value for A3A2 0 1 1 1 D7
1 0 0 0 D8
- One Decoder can be therefore
1 0 0 1 D9
A3A2 = 10
used with inputs: A3A2 1 0 1 0 D10
D4
A0 2x4 D5
A1 Decoder D6
D7
A2 2x4
A3 Decoder D8
A0 2x4 D9
A1 Decoder D10
D11
D12
A0 2x4 D13
A1 Decoder D14
D15
B0
B1
A0 B2 Y0
A1
QUAD
B3 Y1
A2 A>B
4-bit GT A0 2X1 Y2
A3
A<B
Magnitude LT A1 MUX Y3
B0 A=B
Comparator EQ A2
B1
B2
A3
B3 For So=1, A
S0 is selected,
For So=0, B
is selected
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0