VLSI Design

Department of ECE

(NAAC Accredited “A++” Grade University)

 Microprocessor/DSP
The most practical method to solve a system design problem
• Use a standard microprocessor or digital signal processor (DSP).
• Single-chip microprocessors with built-in RAM and EEROM/EPROM.
• Provide great flexibility because systems can be upgraded in the field through
software patches
• Microprocessor should have a wide range of clock speeds, memory sizes, and
analog I/O capability (ADCs) in a small package.
• PIC family of processors.
• Digital Signal Processors.
• Analog Devices and Texas Instruments .
Limitations
The cost, speed, or power dissipation of a microprocessor may not meet system
goals and an alternative solution is required. Software upgradation cost.
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 Programmable Logic

PLA : AND plane and OR Plane are

programmable.

PAL : AND plane is programmable and

OR plane is fixed.

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 Programmable Logic (PLA)

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 Programmable Logic (PAL)

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 Design Approaches in VLSI Design

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 FPGA
• A field-programmable gate
array (FPGA) is a semiconductor
device that can be configured by
the customer or designer after
manufacturing—hence the name
“field-programmable”.
• Programmed using a a source
code in a hardware description
language (HDL)

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 Programmable Logic
1.Rectangular array of configurable logic
blocks (CLBs) capable of implementing a
variety of logic functions.
2.Programmable interconnection
resources or wiring tracks in simple
wires to route the signals between the
CLBs.
3.Switches to connect the horizontal and
vertical wiring tracks.
4.Configurable I/O blocks for signal
conditioning at the chip input and output
pins.
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 Configurable Logic Block
• A Lookup table is a small black
box to implement its intended
function taking many inputs
giving a single output.

• Users can configure the lookup

tables as read/write RAM cells.

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 Look up Table

The Column F is stored in the SRAM Cells.

For a complex digital system (circuit) to be realized in an FPGA, each of its logic
function in the circuit must be small enough to fit within the CLB.

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 CLB Properties
1.A large size logic block implements more logic and hence requires less number
of
logic blocks to implement functionality on the FPGA. On the other hand, a large
logic block will consume more space on the FPGA. So optimal size of logic block
is one that optimally uses lesser number of logic blocks for functionality
implementation while consuming as little space as possible.
2.Active logic area is generally less than total logic area due to presence of
programmable connections. Total logic area is sum of active logic area and area
consumed by programmable connections.
3.Routing area in an FPGA is typically more than the active area. It is 50 per cent
of total area in an FPGA.
4.In case of lookup table based FPGA, a 4-input lookup table gives best results in
terms of logic synthesised and area consumed.
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 FPGA Routing Techniques
• Routing architecture comprises of programmable switches and wires.
• Routing provides connection between I/O blocks and logic blocks, and
between one CLB and another CLB.
Four types of wire segments available:
1. General purpose segments, the ones
that pass through switches in the switch
block.
2. Direct interconnect: ones which connect
logic block pins to four surrounding
connecting blocks.
3. Long line: high fan out uniform delay
connections.
4. Clock lines: clock signal provider which
runs all over the chip.
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 Programmable switching methodologies
SRAM based switches

Two applications of SRAM cells

• one to control the gate nodes of
pass-transistor switches
• the select lines of multiplexers that
drive logic block inputs.

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 Programmable switching methodologies
Anti-Fuse Technology • Two conductors (polysilicon and diffusion wires)
are separated by a dielectric material (ONO –
oxide nitride oxide) which normally exhibits high
impedance. An anti-fuse is normally high
resistance (>100 MΩ).
• On application of appropriate programming
voltages across the dielectric, it breaks down and
current flows and a permanent low resistance
(200–500 Ω) connection is made between the
conductors.
• This can be understood as a permanent connection
between two wire segments.
• This is contrast to SRAM switching technology which
can be re-programmed any time. The process is
Friday, January 24, 2020 irreversible.
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 Configurable I/O
Blocks
A Configurable I/O Block is used to bring signals onto the chip and send them back off again.

• Consists of an input buffer and an output buffer

with three state and open collector output
controls.
• Typically, there are pull up resistors on the
outputs and sometimes pull down resistors. The
polarity of the output can usually be programmed
for active high or active low output and often the
slew rate of the output can be programmed for
fast or slow rise and fall times.
• In addition, there is often a flip-flop on outputs so that
clocked signals can be output directly to the pins
without encountering significant delay
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 Gate Array and Sea of gates Design
If Designers want to keep the non-recurring engineering cost as low as possible ???

• Engineering Design Costs.

• Prototype Design Costs
Solution :
Gate Arrays :
• To construct a common base array of transistors and personalize the chip by
altering the metallization (metal and via masks) that is placed on top of the
transistors.
• Popular methods of designing semicustom ASICs.
• Sea-of- Gate Arrays (SOG) – A Sub Class.

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 Gate Array and Sea of gates (SOG) Design

• SOG can be Re-Programable or designed as a Fixed Logic.

• The system-on-chip can be comprised of a set of fixed functions (e.g., a
processor, RAM, and dedicated accelerators), and an SOG area.
• Rows of nMOS and pMOS transistors are arrayed in the SOG
portion of the chip. Each logic row consists of an n row and p
row.

• Grounding the gate of the nMOS transistor or connecting the

gate of the pMOS transistor to the VDD rail provides isolation
between gates.

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 Gate Array and Sea of gates (SOG) Design
A gate array structure that uses groups of
three transistor pairs.
• SOG structure programmed to
be a 3-input NAND gate.
• The nMOS and pMOS
transistors at each end isolate
the gate.
• Personalization of this SOG
structure commences at
contact and metal1 masks, and
can continue up for all metal
a small SOG area remains useful for layers available in the process.

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 Cell-Based Design
• Cell-based design can deliver smaller, faster, and lower-
power chips than FPGAs but has high NRE costs to
produce the custom mask set.
• As compared to full- custom design, cell-based design offers
much higher productivity because it uses predesigned cells with
layouts.

• Small-scale integration (SSI) logic (NAND, NOR, XOR,

AOI, OAI, inverters, buffers, registers)
• Memories (RAM, ROM, CAM, register files)
• System level modules such as processors, protocol
processors, serial interfaces, and bus interfaces
• Possibility of mixed-signal and RF modules

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 Cell-Based Design
• Usually standard cells are a fixed height with power
and ground routed respectively at the top and
bottom of the cells.
• A single row of nMOS transistors adjacent to GND
(ground) and a single row of pMOS transistors adjacent
to VDD (power) are normally used.
• The polysilicon gate is connected from nMOS transistor
to pMOS transistor .
• Decisions about the sizes of transistors have to be made.
Following this decision, the cells are almost completely
defined by the process design rules.

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 Cell-Based Design
• The height of the cell is defined by the sum of the
nMOS and pMOS transistor widths, the separation
on n and p regions, the spacing to VDD and GND
busses, and the width of these busses.
• The horizontal pitch is defined by the poly-to-
metal2 contacted pitch,

• Options to standard cells include routing the clock

with the power and ground busses and routing
multiple supply voltages to each cell.
• This technique is sometimes used to reduce
power by connecting gates that are not in the
critical path to a lower than normal supply
voltage because the power drops with the
square of the supply voltage
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 Typical Standard Cell Library

• In Medium Scale Integration

(MSI) functions such as adders,
multipliers, and parity blocks
used to be supplied as cells,
• Synthesis engines commonly
construct these from base-level
Small Scale Integration (SSI)
gates in current design systems.
• Design time.
• Power.
• Delay.

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 Cell-Based Design
• A 1x (normal power) cell commonly is defined to use the widest
transistors that fit within the vertical pitch of the standard cell.
• 2x and larger (high power) cells use wider transistors to deliver more
current. They must fold the transistors to fit within the cell; this comes at
the expense of increased cell width.

• Low Power Cells :

• Gates are often available in low power versions as well. These cells
use minimum-width transistors to reduce capacitance. Low-power
cells tend to be slow because of the wire capacitance they must drive.
Although they do not save area, they do reduce power consumption
on noncritical paths.

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 Cell-Based Design
• Application : Memories of assorted sizes
• From a graphical user interface (Front end Tool) using sophisticated
libraries.
• The generators yield the physical layout
• Complete data sheet indicating access times, cycle times, and power
dissipation.

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 Full Custom Design
Custom mask layout
• A designer sits in front of a graphics display running an interactive editor and pieces
designs together at the geometry level one rectangle at a time. This work is sometimes
called polygon pushing.
• The transistors, contacts, wires, and ports (points of connection).
• Generating of layout by software generators is called Silicon Compilation.
• An algorithm can be written to place the cells on the standard cell grid. In addition, a
linked algorithm can be written to generate a gate netlist in an HDL. In this way, both
the physical and structural design are captured. The behavior can be represented by
an HDL function or module call. Such custom placement can shorten wire lengths and
thus improve speed and power

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 SoC

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