High Level Digital Design &

Testing (HLDDT)
 Course Content

• Verilog HDL (1st Internal)

• VHDL (2nd Internal)

• Testing (3rd Internal)

12/08/21 04:22 Verilog 2

 References
• Verilog HDL
– Samir Palnitkar

• VHDL Primer
– J Bhasker

• VHDL
– Douglas Perry

• Digital system Testing & Testable Design

– Miron Abrammovici
– Melvin A Breuer
– Arthur D Friedman

12/08/21 04:22 Verilog 3

 Internal Marks Distribution
• Internal Marks (Best TWO) - 15 Marks
• Assignments & Attendance - 15 Marks
• Mini Project - 15 Marks
• Class Presentation - 05 Marks
-----------------------------
• Total Internal Marks - 50 Marks
------------------------------

• External - 50 Marks

• Note :
No retest will be given.

12/08/21 04:22 Verilog 4

 Typical Design Flow
Design Specification

RTL Description

Functional verification

Logic Synthesis

Gate Level Netlist

Logical Verification

Floorplanning Automatic PR

Physical Layout

Layout Verification

Implementation

12/08/21 04:22 Verilog 5

 Verilog - Wide Range of Modeling Levels
always #($dist_poisson (seed, 32))
begin
if $q_full (qid)
Architectural $q_remove (qid, job, job_id, status);
else
-> fill_queue;
end

always @( fetch_done)
begin
casez ( IR [7:6] )
Algorithmic 2’ b00 : LDA (acc, IR[ 5:0 ] );
2’ b01 : STR (acc, IR [ 5:0 ] );
Increasing 2’ b10 : JMP (IR [ 5:0 ] );
level of 2’ b11 : ; / / NOP
abstraction endcase
end

assign rt1 = ( i1&buserr ) | zero;

RTL assign sub = rt1^ |op;
assign out1 = i1&i2|op;

behavioral
Gate (non-structural)

gate/switch
(structural)
Switch

12/08/21 04:22 Verilog 6

 Range of Use

Graphical Specification
Specification Textual
Description of the system design
Tables
Behavioural System Design
VHDL System design
Validation Modeling system behaviour

Logic Design Logic design

RTL VHDL
Modeling the structure
Simulation
Validation Test bench
Stimuli/Response
Netlist VHDL Circuit Design Circuit design
Automatic conversion of structural description
Validation
Validation
Layout Check function through simulation
Provide input stimuli
Validation Check expected response

12/08/21 04:22 Verilog 7

 Basic Building Block in Verilog
module module_name (port list);
Port declarations
Parameter declarations (Interface)

‘includedirectives (Add on)

Variable declarations
Assignments
Lower level module instantiation
Initial and always block
Tasks and functions (Body)

endmodule

12/08/21 04:22 Verilog 8

 Example

In_1 Sum

In_2
1-bit
full-adder
C_In Carry

Sum = in_1 xor in_2 xor c_in

carry = (in_1 and in2) or (in_2 and c_in) or (in_1 and c_in)

12/08/21 04:22 Verilog 9

 Behaviour Model
module full_adder (sum, carry, in1, in2, cin);

input in1, in2, cin;

output sum, carry;
reg sum,carry;

always @(in1 or in2 or cin)

begin
sum = in1 ^ in2 ^ cin;
carry = (in1 & in2 ) | (in1 & cin) | (in2 & cin);
end

endmodule

12/08/21 04:22 Verilog 10

 Dataflow Model
module full_adder (sum, carry, in1, in2, cin);

input in1,in2, cin;

output sum, carry;

assign {carry,sum} = in1 + in2 + cin ;

endmodule

12/08/21 04:22 Verilog 11

 Structural Model
module full_adder (sum, carry, in1, in2, cin);

input in1,in2, cin;

output sum, carry;
in1 x1
wire x1,a1,a2,a3,o1,o2; in2 sum
cin
xor(x1,in1,in2);
xor(sum,x1,cin);
and(a1,in1,in2); in1
a1
and(a2,in1,cin); in2
o1
and(a3,in2,cin); in1
a2 carry
or(o1, a1,a2); cin
or(carry,o1,a3); in2 a3
cin
endmodule

12/08/21 04:22 Verilog 12

Basic Concepts
 Basic Concepts
• Lexical Conventions

• Data Types

• System Tasks & compiler directives

12/08/21 04:22 Verilog 14

Lexical Conventions
 Lexical Conventions
• Whitespace & Comments
• Operators
• Number specification
– Sized number
– Unsized number
– X or Z values
– Negative numbers
– Underscore characters & question marks
• Strings
• Identifiers & keywords
• Escaped identifies

12/08/21 04:22 Verilog 16

 Lexical Conventions
• Blank space - \b

• Tabs - \t

• Newline - \n

• Comments
– One line comments - //
– Multiple line comments - /* */

12/08/21 04:22 Verilog 17

 Operators

• Three types

– Unary operator ( a = ~b )

– Binary operator ( a = b && c )

– ternary operator (a=b?c:d)

12/08/21 04:22 Verilog 18

 Number Specification - Sized Number

Sized number • Base format

<size>‘<base format> <number> – Binary (b or B)
– Octal (o or O)
– Decimal ( d or D)
Example – Hexa-decimal (h or H)
4’b1010 //4-bit binary #
16’d255 //16-bit decimal #
• Number
9’o123 //9-bit Octal #
– 0 - 9, a - f
12’habc //12-bit hexadecimal #

12/08/21 04:22 Verilog 19

 Number Specification - Unsized Number

Unsized number • Base format

‘<base format> <number>
– Binary (b or B)
– Octal (o or O)
– Decimal ( d or D)
Example
– Hexa-decimal (h or H)
’b1010 //32-bit binary #
’d255 //32-bit decimal #
• Number
‘o123 //32-bit Octal #
– 0 - 9, a - f
’habc //32-bit hexadecimal #

12/08/21 04:22 Verilog 20

 Number Specification

Example
12’h13x
//12-bit hex number; last 4 bit
Unknown value -X // unknown value

High Impedance -Z 6’hx

//6-bit hex number
// ”xxxxxx”

32’bz
//32-bit binary number
// 32 bit “z”

12/08/21 04:22 Verilog 21

 Number Specification - Negative Number

Negative number • Base format

-<size>‘<base format><number>
– Binary (b or B)
– Octal (o or O)
– Decimal ( d or D)
Example – Hexa-decimal (h or H)
-4’b1010 //4-bit binary #
-16’d255 //16-bit decimal #
• Number
-9’o123 //9-bit Octal #
– 0 - 9, a - f
-12’habc //12-bit hexadecimal #
16’d-255 //16-bit invalid decimal #

12/08/21 04:22 Verilog 22


• Under score character
– It is allowed anywhere in the
number except starting of the
number
Number Specification
• question marks
– “?” Denotes High Impendance
value

12/08/21 04:22 Verilog 23

 Strings
Sequence of character enclosed within double quotes

Example

“hello world” //valid string

“a/b” // valid string

12/08/21 04:22 Verilog 24

 Exercises

• Are the following, legal strings? If not, write

the correct strings.

– “this is a string displaying the % sign”

– “out = in1 + in2”

– “please ring a bell \007”

– “this is a backslash \ character \n”

12/08/21 04:22 Verilog 25

 Identifiers & keywords
• Verilog is case sensitive

• All verilog keywords are lower case

– Example:
• input //verilog keyword
• INPUT //a unique name(not a keyword)

• Identifiers
– Identifiers are names assigned to modules, signals, variables..
– They must begin with an alphabetic character or underscore
– Example:
• addbit, sum, a$b, _multi etc

12/08/21 04:22 Verilog 26

 Escaped Identifiers
• Identifier begins with “\” and ends with white space (blank
space or tab or lines).

Example
\a + b +c
\ ** my name **

12/08/21 04:22 Verilog 27

 Exercises

• Are these legal identifiers?

– system1

– 1reg

– $latch

– exec$

12/08/21 04:22 Verilog 28

Data Types
 Data Types
• Value set
• Nets
• Registers
• Vectors
• Integer, real & time register
• Arrays
• Memories
• Parameters
• Strings

12/08/21 04:22 Verilog 30

 Value set

Zero, Low, False, Logic Low, Ground,

‘0’ VSS, Negative Assertion

One, High, True, Logic High, Power,

‘1’ VDD, VCC, Positive Assertion

X, Unknown: Occurs at Logical

‘X’ Conflict Which Cannot be Resolved

HiZ, High Impedance, Tri-Stated,

‘Z’ Disabled Driver (Unknown)
0

12/08/21 04:22 Verilog 31

 Value set
0  logic 0 Supply 1 strongest driving
Strong 1 driving
1  logic 1 Pull 1 driving
X  unknown value Large 1 storage
Weak 1 driving
Z  high impedance, floating Medium 1 storage
state Small 1 storage
Highz 1 weakest 1 high imp
Highz 0 weakest 0 high imp
Small 0 storage
Medium 0 storage
Weak 0 driving
Large 0 storage
Pull 0 driving
Strong 0 driving
Supply 0 strongest 0 driving

12/08/21 04:22 Verilog 32

 Nets

Various net types are available for modeling design-specific and

technology-specific functionality
Net Function Verilog Net Type

Standard wire, tri

Wired OR wor, trior
Wired AND wand, triand
Capacitive trireg
Pullup tri1
Pulldown tri0
Power supply1
Ground supply0

nets that are not

explicitly declared module test_fixture ;
default to single-bit reg r_in, s_in;
nets of type wire
rs_ff d1(out, outnot, r_in, s_in);
. . .
endmodule

12/08/21 04:22 Verilog 33

 Registers
• Storage elements
– Variable that can hold value. (not HW Register)

Syntax

reg register_name;

12/08/21 04:22 Verilog 34

 Vectors
Syntax Example

wire [vector_length] vector_name wire a //default length 1

reg [vector_length] vector_name wire [7:0] bus //length 8 bit
reg [0:7] addr //length 8 bit

12/08/21 04:22 Verilog 35

 Integer
 Integers are at least host machine Example
size (or 32-bits wide).
Integer counter;

 Integers are signed.

 Integers are declared using the

keyword integer

12/08/21 04:22 Verilog 36

 Real
 A real data type holds a floating point
number in IEEE format. Example
real delta;
 Reals are at least 32-bit wide.
delta = 4e10;
 Reals are declared using the keyword
real delta = 3.14;

 Real cannot have range declaration

 Default value is ‘0’

 When real ia assigned to integer, the

real number is rounded to nearest
integer value.

12/08/21 04:22 Verilog 37

 Time
• Width of time register is Example
implementation specific but it at
least 64 bits
time save_sim_time
• Simulation time is measured in save_sim_time = $time
simulation seconds

12/08/21 04:22 Verilog 38

 Arrays
• Arrays are allowed in verilog for
reg, integer, time & vector
Example
register data types
reg port_id [0:7]
• Multi-dimensional arrays are not reg [4:0] port_id [0:7]
allowed. integer counter [7:0]
time chk_pnt [0:100]
Syntax

data_type array_name [Range]

12/08/21 04:22 Verilog 39

 Memories
• Each element in array is known as Example
a word

reg mem [0:1023]

• Each word can 1-bit or more bits
reg [7:0] mem [0:1023]
Mem[512]
• It is important to differentiate
between n 1-bit register and one n-
bit register

12/08/21 04:22 Verilog 40

 Parameters
• Verilog allows constant to be Example
defined in a module by the
keyword parameter
parameter port_id = 5;
Syntax parameter mem_width = 256
parameter constant_name = value

12/08/21 04:22 Verilog 41

 Strings
• Each character in the string takes Example
up 8 bits(1 byte)

reg [8 * 11:1] string_value

• If width of register > string, fills
LSB with Zeros string_value = “hello world”;

• If width of register < string,

truncates LSB bits.

12/08/21 04:22 Verilog 42

System Task & Compiler
Directives
 System Task & Compiler Directives
System task • $write
• • $strobe
$display
• • $random
$monitor
• • $readmemb
$monitoron
• • $readmemh
$monitoroff
• $stop Compiler directives
• $finish • ‘define
• $fopen • ‘include
• $fdisplay • ‘ifdef
• $fmonitor • ‘timescale
• $fclose • ‘ifdef - ‘else - ‘endif

12/08/21 04:22 Verilog 44

Gate Level Modeling
 Gate Level Modeling

• Gate Types

• Gate Delay

12/08/21 04:22 Verilog 46

Gate Types
 Gate Types
Logic Gates
– and nand
– or nor
– xor xnor
Buffers
– buf bufif1 bufif0,
– not notif1 notif0
Transistors
– nmos rnmos
– pmos rpmos
– cmos rcmos,
– tran rtran
– tranif0 rtranif0
– tTranif1 rtranif1

12/08/21 04:22 Verilog 48

 AND & NAND Gate

in1 in1
out out
in2 in2

and 0 1 x z nand 0 1 x z
0 0 0 0 0 0 1 1 1 1
1 0 1 x x 1 1 0 x x

x 0 x x x x 1 x x x
z 0 x x x z 1 x x x

12/08/21 04:22 Verilog 49

 OR & NOR Gate

in1 in1
out out
in2 in2

or 0 1 x z nor 0 1 x z
0 0 1 x x 0 1 0 x x
1 1 1 1 1 1 0 0 0 0

x x 1 x x x x 0 x x
z x 1 x x z x 0 x x

12/08/21 04:22 Verilog 50

 XOR & XNOR Gate

in1 in1
out out
in2 in2

xor 0 1 x z xnor 0 1 x z
0 0 1 x x 0 1 0 x x
1 1 0 x x 1 0 1 x x
x x x x x x x x x x
z x x x x z x x x x

12/08/21 04:22 Verilog 51

 BUF, BUFIF0 & BUFIF1 Gate
buffer

In 0 1 x z
buffer input output
out 0 1 x x

control
bufif1 0 1 x z
0 z 0 L L
1 z 1 H H bufif1 input output

input x z x x x
z z x x x
control

control
bufif0 0 1 x z

0 0 z L L
input output
1 1 z H H bufif0
input
x x z x x
z x z x x control

12/08/21 04:22 Verilog 52

 NOT, NOTIF0 & NOTIF1 Gate
not

In 0 1 x z
not input output
out 1 0 x x

control
notif1 0 1 x z

0 z 1 H H
1 z 0 L L notif1 input output

input x z x X x
z z x x x
control

control
notif0 0 1 x z

0 1 z H H
input output
1 0 z L L notif0
input
x x z x x
z x z x x control

12/08/21 04:22 Verilog 53

 PMOS & NMOS Transistor
control
pmos 0 1 x z data out

0 0 z L L
data pmos
1 1 z H H
x x z x x control
z z z z z

control
nmos 0 1 x z data out
0 z 0 L L
1 z 1 H H nmos
data
x z x X x control
z z z z z

12/08/21 04:22 Verilog 54

Gate Delays
 Gate Delays
• Rise time delay

• Fall time delay

• Turn-off delay

• Minimum value delay

• Typical value delay

• Maximum value delay

12/08/21 04:22 Verilog 56

 Rise Time & Fall Time
Rise Time Fall Time
Gate out transition to a ‘1’ Gate out transition to a ‘0’
from another value from another value

1, x or z

0, x or z

rise_time fall_time

12/08/21 04:22 Verilog 57

 Turn-off Delay

Turn-off Delay
Gate output transition to the high impedance value from
another value

0, 1 or x z

12/08/21 04:22 Verilog 58

 Example of delays
Delay time for all transitions
and #(delay_time) a1(out,in1,in2);
and #(5) a1(out,in1,in2);

Rise & Fall time delay

and #(rise_val, fall_val) a1(out,in1,in2);
and #(5, 5) a1(out,in1,in2);

Rise, Fall & turnoff time delay

and #(rise_val, fall_val, turnoff_val) a1(out,in1,in2);
and #(5, 5, 5) a1(out,in1,in2);

12/08/21 04:22 Verilog 59

 Minimum & Typical Value Delay
Minimum Value Delay Typical Value Delay
Minimum delay value that the Typical delay value that the
designer expect gate to have. designer expect gate to have.

Maximum Value Delay

Maximum delay value that
the designer expect gate to
have.

Example
and #(2:3:4, 3:4:5, 5:6:7) a3 (out, in1, in2)

12/08/21 04:22 Verilog 60

 Example for Delay Model

#10 out = in1 & in2; out = #10 in1 & in2;

12/08/21 04:22 Verilog 61

Data flow Modeling
 Data flow Modeling

• Continuous Assignment
– Implicit Continuous Assignment

• Delays
– Regular Assignment Delay
– Implicit Continuous Assignment Delay
– Net Declaration Delay

12/08/21 04:22 Verilog 63

 Continuous Assignment
• assign out = in_1 & in_2;
• assign {carry, sum} = in_1 + in_2 + Carry_in;

12/08/21 04:22 Verilog 64

 Implicit Continuous Assignment

// Regular continuous assignment

wire out
assign out = in1 & in2;

//Implicit Continuous Assignment

wire out = in1 & in2;

12/08/21 04:22 Verilog 65

 Regular Assignment Delay

assign #10 out = in1 & in2;

in1

in2

out

10 20 30 60 70 80 85

12/08/21 04:22 Verilog 66

 Implicit Continuous Assignment Delay

// Regular continuous assignment

wire out
assign #10 out = in1 & in2;

//Implicit Continuous Assignment

wire #10 out = in1 & in2;

12/08/21 04:22 Verilog 67

 Net Declaration Delay

//Net Delays
wire #10 out;
assign out = in1 & in2;

// Regular continuous assignment

wire out
assign #10 out = in1 & in2;

12/08/21 04:22 Verilog 68

Operators
 Operators
Arithmetic Relational
– + : Add – == : Equal
– - : Subtract – != : Not equal
– * : Multiply – > : Greater than
– / : Divide (powers of 2) – < : Less than
– % : Modulus (powers of 2) – <= : Less than or equal
Bitwise - right to left – >= : greater than or equal
– ~ : Invert Reduction (Not available in VHDL)
– & : AND • & : AND all bits
– | : OR • ~& : NAND all bits
– ^ : XOR • | : OR all bits
– ~^ : XNOR
• ~| : NOR all bits
Shift (available in VHDL’93) • ^ : XOR all bits
– >> : Right shift
– << : Left shift

12/08/21 04:22 Verilog 70

Behavioral Modeling
 Behavioral Modeling
• Structured Procedure • Level sensitive timing control
– Initial Statement • Conditional statements
– Always Statement
– if - then - else statement
• Procedural Assignment
– Blocking Assignment
• Case statement
– Nonblocking Assignment – Case keyword
• Timing Control – Casex keyword
– Casez keyword
• Delay - Based Timing Control
– Regular Delay Control • Loop Statement
– Intra - assignment Delay control – While Loop
– Zero delay control – For Loop
• Event - Based Timing control – Repeat Loop
– Regular event control – Forever Loop
– Named event control
• Sequential Blocks & Parallel
– Event OR control
Blocks

12/08/21 04:22 Verilog 72

 Structured Procedure
initial Statement Syntax
• Initial block starts at 0 initial
simulation time
begin
• Executes exactly only -------
once -------
end
• Multiple Initial blocks
executes concurrently at
time 0

12/08/21 04:22 Verilog 73

 Initial Statement - Example
module stimulus
Time statement execution Time
reg x, y, a, b, m;
m = 1’b0; 0 m = 1’b0
Initial
begin
5 a = 1’b1
#5 a = 1’b1; 10 x = 1’b0
#25 b = 1’b0;
end 30 b = 1’b0
Initial 35 y = 1’b1
begin
#10 x = 1’b0; 50 $finish
#25 y = 1’b1;
end
Initial
#50 $finish

endmodule

12/08/21 04:22 Verilog 74

 Structured Procedure
always Statement Syntax
• It executes in looping always (optional)
fashion
-----
-----
-----

12/08/21 04:22 Verilog 75

 Always Statement - Example
module clock_gen;
reg clock;
initial
Clock = 1’b0;

always
#10 clock = ~clock;

initial
#1000 $finish;

endmodule

12/08/21 04:22 Verilog 76

 Procedural Assignment
• The value placed on a variable remain unchanged until
another procedural assignment updates the variable with
different value.

• Syntax
<assignment>
::= <lvalue> = <expression>

• Two types of procedural assignment statements

– Blocking assignment
– Nonblocking assignment

12/08/21 04:22 Verilog 77

 Blocking Assignment
• The = operator is used to specify blocking statement

• RHS has more bits than the LHS, then MSB is truncated

• RHS has fewer bits than the LHS, then MSB is padded with
Zeros

12/08/21 04:22 Verilog 78

 Blocking Assignment - Example
initial Time = 0
begin x = 0 to statement
x = 0; y= 1; z = 1; reg_b = reg_a
count = 0;
reg_a = 16’b0; Time = 15
reg_b = reg_a; reg_a[2] = 0
#15 reg_a[2] = 1’b1;
#10 reg_b[15:13] = {x, y, z} Time = 25
count = count +1; reg_b[15:13] = {x, y, z}
end count = count + 1

12/08/21 04:22 Verilog 79

 Nonblocking Assignment
• The <= operator is used to specify blocking statement

12/08/21 04:22 Verilog 80

 Nonblocking Assignment Example
initial Time = 0
begin x = 0 to statement
x = 0; y= 1; z = 1; reg_b = reg_a &
count = 0; count = count + 1
reg_a = 16’b0;
reg_b = reg_a; Time = 10
#15 reg_a[2] <= 1’b1; reg_b[15:13] = {x, y, z}
#10 reg_b[15:13] <= {x, y, z}
count <= count +1; Time = 15
end reg_a[2] = 0

12/08/21 04:22 Verilog 81

 Procedural Assignment Example

Blocking statement Nonblocking statement

always @ (posedge clock) always @ (posedge clock)

a = b; a <= b;

always @ (posedge clock) always @ (posedge clock)

b = a; b <= a;

12/08/21 04:22 Verilog 82

 Timing Controls
• Three methods of timing control
– Delay - based timing control
– Event based timing control
– Level - sensitive timing control

12/08/21 04:22 Verilog 83

 Delay - based timing control
• Three types of delay control for procedural
assignments.
– Regular delay control
– Intra - assignment delay control
– Zero delay control

12/08/21 04:22 Verilog 84

 Regular delay control
parameter latency = 20;
parameter delta = 20;
reg x, y, z, p, q; No
Nodelay
delaycontrol
control
initial
begin Delay
Delaycontrol
controlwith
withnumber
number
x = 0;
#10 y = 1;
Delay
Delaycontrol
controlwith
withIdentifier
Identifier
#latency z = 0;
#y x = x+1;
#(latency + x) p = 1; Delay
Delaycontrol
controlwith
withexpression
expression
#(4:5:6) q = 0;
end Delay
Delaycontrol
controlwith
withmin,
min,typ
typ&&max
max

12/08/21 04:22 Verilog 85

 Intra - assignment delay control
Initial
Takes
Takesvalue
valueofofxx&&yyatattime
time==00
begin
x = 0; z = 0;
y = # 5 x +z Assigns
Assignsthe
theexpression
expressionafter
after55time
timeunits
units
end

// same as above
Initial
begin
x = 0; z = 0;
temp_xz = x + z;
#5 y = temp_xz;
end

12/08/21 04:22 Verilog 86

 Zero Delay Control
Initial
begin
x = 0;
z = 0;
end

Initial
begin
#0 x = 0; The
Theorder
orderofofexecution
executionisisnot
notdeterministic
deterministic
#0 z = 0;
end

12/08/21 04:22 Verilog 87

 Event - Based Timing Control
• Four types of event based timing control
– Regular event control
– Named event control
– Event OR control
– level - sensitive timing control

12/08/21 04:22 Verilog 88

 Regular event control

@ symbol is used to specify an event control

Statement is executed on changes in signal value.

Event
Eventcontrol
control
@ (clock) q = d;
@ (posedge clock) q = d;
@ (negedge clock) q = d;
q = @(posedege clock) d;

12/08/21 04:22 Verilog 89

 Named Event Control
event received_ data;

always @ (posedge clock)

begin Named
NamedEvent
Eventcontrol
control
if (last_data_packet)
 received_data
end

always @(received_data)

12/08/21 04:22 Verilog 90

 Event OR control

always @(reset or clock)

Event
EventOR
ORcontrol
control
begin
If (reset)
q = 1’b0;
else if (clock)
q = d;
end

12/08/21 04:22 Verilog 91

 Level Sensitive Timing Control

The keyword wait is used for level-sensitive constructs

always
wait (clock) Level
Levelsensitive
sensitiveevent
event
count = count + 1;

12/08/21 04:22 Verilog 92

 Conditional Statement

If statement construct

If (<expression>) true_statement; If (<expression>) true_statement;

else false_statement;

If (<expression>) true_statement1;
else if true_statement2;
else if true_statement3;
else default_statement;

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 Case statement -1

case (<expression>)
Alternative1: statement1;
Alternative2: statement2;
Alternative3: statement3;
-----
-----
default: default_statement;
end case

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 Case statement - Example
Case ({s1,so}) 2’bz0 : out = 1’bz;
2’bz1 : out = 1’bz;
2’b00 : out = in1; 2’bzz : out = 1’bz;
2’b01 : out = in2; 2’b0z : out = 1’bz;
2’b10 : out = in3;
2’b1z : out = 1’bz;
2’b11 : out = in4;

2’bx0 : out = 1’bx; default : $display(“unspecified

control signal”);
2’bx1 : out = 1’bx;
2’bxz : out = 1’bx;
2’bxx : out = 1’bx; endcase
2’b0x : out = 1’bx;
2’b1x : out = 1’bx;
2’bzx : out = 1’bx;

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 Case statement - 2
Casez statement
Treats “z” values in the case alternative as don’t care. All bits
positions with z can also represented by “?’ in that position.

Casex statement
Treats all “x” & “z” values in the case item as don’t cares

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 Loops Statement
• Four types of loop statements
– While loop
– For loop
– Repeat loop
– Forever loop

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 While statement
Syntax

while expression
begin
statement1
statement2
statement3
end

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 While statement - Example

initial
begin
count = 0;
while (count <128)
begin
count = count + 1;
end
end

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 For loop statement
Syntax
for (initialise; condition; incr/decr)

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 For loop statement - Example

for (count=0; count<128; count = count +1)

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 Repeat Loop
Repeat (constant / variable / signal)

Note:
In case of variable or signal, it is evaluated only when
the loop starts and not during the loop execution

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 Repeat Loop - Example

count = 0;
repeat(128)
begin
count = count + 1;
end

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 Forever loop Statement
• It is used in conjunction with timing control constructs.

forever #time value = expression

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 Forever loop Statement - Example

Clock = 1’b0; Infinite

Infiniteloop
loop
Forever #10 clock = ~clock;

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 Sequential block
• Statement in sequential block is executed one after the
another.(expect the nonblocking assignment
statements)

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 Sequential block - Example

Sequential clock without delay Sequential clock with delay

initial initial
begin begin
x = 1’b0; x = 1’b0;
y = 1’b1; #5 y = 1’b1;
z = {x, y}; #10 z = {x, y};
w = {x, y}; #20 w = {x, y};
end end

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 Parallel Block
• It is specified by the keyword fork & join

• Statements in parallel blocks are executed concurrently

• Ordering is controlled by delay statements.

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 Parallel Block - Example

initial
fork
x = 1’b0;
#5 y = 1’b1;
#10 z = {x, y};
#20 w = {x, y};
join

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 Special Features of Blocks
• Three special features
– Nested blocks
– Named blocks
– Disabling named blocks

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 Nested blocks

initial Nesting
Nestingofofsequential
sequential&&parallel
parallelblocks
blocks
begin
x = 1’b0;
fork
#5 y = 1’b1;
#10 z = {x, y};
join
#20 w = {x, y};
end

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 Named Blocks

initial
sequential
sequentialblocks
blocks
begin: block1
Integer
Integerisisstatic
static&&local
localtotoblock
block11
integer i; Can
Canbe
beaccessed
accessedby byhierarchical
hierarchicalname,
name,top.block1.i
top.block1.i
----
----
end

parallel
parallelblocks
blocks
initial
register
registerisisstatic
static&&local
localto
toblock
block22
fork: block2 Can
Canbe
beaccessed
accessedby byhierarchical
hierarchicalname,
name,top.block2.i
top.block2.i
reg i;
-----
-----
join

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 Disabling Named Blocks

Disable provides a way to terminate the execution of a block

Similar to c break, except that it disables the named block in the design

Example
Flag = 8’b 0010_0000;
i = 0;
begin: block1
while (I<8)
begin
if (flag[I])
begin
$display(“encountered the TRUE condition”)
disable block1;
end
I = I +1;
end

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Task & Functions
 Task & Functions
• Tasks have input, output, inout arguments.

• Functions have input arguments

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Functions
A function can enable another
function but not another task
Functions always executes in 0
simulation time
Functions must not contain any
delays, event, or timing control
statements
Functions must have at least one
input arguments. They can have
more than one input
Functions always return a single
value. They cannot have output or
input arguments
12/08/21 04:22
Functions Vs Tasks
Tasks
A task can enable other tasks &
functions
Tasks may executes in non-zero
simulation time
Tasks may contain delays, event, or
timing control statements
Tasks may have zero or more arguments
of type input, output or inout
Tasks do not return with a value but
can pass multiple values through output
& inout arguments
Verilog 116
 Task - Example
module operation;
parameter delay = 10;
reg [15:0] a, b;
reg [15:0] ab_and, ab_or, ab_xor;
always @(a or b)
begin
bitwise_oper(ab_and, ab_or, ab_xor, a, b)
end
task bitwise _oper
output [15:0] ab_and, ab_or, ab_xor;
input [15:0] a, b;
begin
#delay ab_and = a & b;
ab_or = a | b;
ab_xor = a ^ b;
end
endtask
endmodule

12/08/21 04:22 Verilog 117

 Functions - Example
module shifter
`define left_shift 1’b0
`define right_shift 1’b1
reg [31:0] addr, left_addr, right_addr;
reg control;
always @(addr)
begin
left_addr = shift(addr, ‘left_shift)
right_addr = shift(addr, ‘right_shift)
end

function [31:0] shift;

input [31:0] address;
input control;
begin
shift = ( control == ‘left_shift) ? (address <<1) : (address >>1);
end
endfunction
endmodule

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Advanced Topics
 Advanced Topics
• Assign & Deassign
• Force & Release
• Defparam statement
• Conditional compilation
– `ifdef, `else, `endif
• Time scales
– `timescale

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 assign & deassign Statement
module edge_dff(q, qbar, d, clk, rst);
output q, qbar
input d, clk, rst;
reg q, qbar

always @(posedge clk)

begin
q = d;
qbar = ~d;
end

always @(rst)
begin
if (rst) Assigns
assign q = 1’b0; Assignsthe
thevalue
valueofofqq==00&&qbar
qbar==11
assign qbar =1’b1;
irrespective
irrespectiveofofvalue
valueofofqq&&qbar
qbar
else
deassign q;
deassign qbar;
end
end module

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 Force & Release Statement
module stimulus; module edge_dff(q, qbar, d, clk, rst);
----- output q, qbar
input d, clk, rst;
---- reg q, qbar
edge_dff dff (q, qbar, d, clk, rst);
------ always @(posedge clk)
----- begin
initial q = d;
qbar = ~d;
begin
end
#10 force dff.q = 1’b1;
#10 release dff.q; always @(rst)
end begin
if (rst)
assign q = 1’b0;
end module
assign qbar =1’b1;
else
deassign q;
deassign qbar;
end
end module

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 Defparam Statement
module hello_world;
parameter id_num = 0;
initial
$display(“hello world id number = %d”, id_num);
endmodule

module top;
defparam w1.id_num = 1, w2.id_num = 2;

hello_world w1 ();
hello_world w2 ();
endmodule

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 Conditional Compilation
• `ifdef statement can appear Syntax
anywhere in the design `ifdef (macro)
– Conditional compile
– Modules
– Blocks
module()
– Declaration &
– other compiler directives `else

• Only one `else part is allowed module()

• Statement always closed by `endif

`endif

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 Time Scales
‘timescale 100ns/1ns
Syntax
`timescale <reference_time_unit> /
<time precision> module dummy1;
reg toggle
1, 10, 100 are valid integer for initial
specifying time unit and time toggle = 1’b0;
precision
always #5
begin
In this module 5 time units = 500ns
toggle = ~toggle;
$display(“%d, in %m toggle =
%b”, $time, toggle);
end
endmodule

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Thank You