Unit I

Microcontroller Basics
 Contents
• Difference between microprocessor and
microcontroller
• CISC Vs RISC design philosophy
• Von-Neumann vs Harvard architecture
• 8-bit and 16-bit microcontroller
• Architecture of microcontroller
• I/O ports
• Stack and use of stack pointer
• Memory structure, Data Memory, Program Memory
and execution of programs
• Different registers (SFR’s)
• Addressing modes
• Timing diagram
 Reference
• AVR ATmega32 Datasheet
• “The AVR Microcontroller and embedded
system”, M. A. Mazidi, S. Naimi
 Introduction to Atmel AVR
• The AVR architecture was conceived by two students Alf-Egil Bogen
and Vegard Wollan at the Norwegian Institute of Technology (NTH).
• The AVR is a modified Harvard architecture 8-bit RISC single chip
microcontroller which was developed by Atmel in 1996.

• The AVR was one of the first microcontroller families to use on-chip
flash memory for program storage, as opposed to one-time
programmable ROM, EPROM, or EEPROM used by other
microcontrollers at that time.
• The AVR is a modified Harvard architecture machine where
program and data is stored in separate physical memory systems
that appear in different address spaces, but having the ability to
read data items from program memory using special instructions.

• The creators of the AVR give no definitive answer as to what the

term "AVR" stands for. However, it is commonly accepted that AVR
stands for Alf (Egil Bogen) and Vegard (Wollan)'s Risc processor“.
It might stands for Advanced Virtual RISC.
AVR Architecture
 Harvard Vs. Von Neumann Architecture

Harvard Architecture Von Neumann Architecture

• Separate memories for data • Same memory holds data, instructions.
and instructions. • A single set of address/data buses
• Two sets of address/data buses between between CPU and memory
CPU and memory
 Modified Harvard Architecture

• There is an addition pathway between CPU and the Instruction memory.

• It allows words in instruction memory be treated as “read-only data”, so

that const data (e.g. text string) can be read into Instruction memory
instead of Data memory.

• This method preserves more data memory for read/write variables.

• Modified Harvard Architecture allows the contents of the Instruction

memory to be treated as if it were data.
 CISC and RISC Comparison
CISC
Complex Instruction Set Computing
Emphasis on hardware
Include multi-clock complex
instructions
Memory-to-memory: “Load” and
“Store” incorporated in instructions
Small code sizes
Transistors (resources) used for
storing complex instructions
RISC
Reduced Instruction Set Computing
Emphasis on software
Include single-clock reduce instruction
only
Register-to-register: “Load” and
“Store” are independent instructions
Large code sizes
Spends more transistors (resources)
on memory registers
 RISC Microcontroller
• Till 1980 Trend was to build increasingly complex CPUs with complex set
of instructions like (CISC).

• (RISC) : Instruction execute in single cycle

“Architecture which reduces the chip complexity by simpler

processing instructions”.

RISC architecture CPUs capable of executing only a very limited

(simple) set of instructions.
 CISC Approach
• Complete the task in few assembly line code

• TASK multiply 2:3, 5:2 locations numbers

and put output in 2:3 location

Command: MULT 2:3, 5:2

• MULT is what is known as a "complex instruction.“

• Instruction doesn`t complete in one cycle execution.

• Processor hardware that is capable of

understanding and executing a series of operations.
 RISC Approach
• RISC processors only use simple instructions
that can be executed within one clock cycle.

• "MULT" command divided into three separate

commands:
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A

• Single Cycle Execution

Reduced Instruction Set Computers Advantages
• Fast Execution of Instructions due to simple instructions for CPU.

• RISC chips require fewer transistors, which makes them cheaper to

design and produce.

• Emphasis on software

• Single-clock, reduced instruction only

• Register to register: “LOAD" and "STORE“ are independent instructions

• Spends more transistors on memory registers

 AVR Microcontroller
• The Atmel AVR core combines a rich instruction
set with 32 general purpose working registers.

• All the 32 registers are directly connected to the

Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single
instruction executed in one clock cycle.

• The resulting architecture is more code efficient

while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
• AVR is a family of 8-bit microntrollers with a large range
of variants differing in:
- Size of program-memory (flash)
- Size of EEPROM memory
- Number of I/O pins
- Number of on-chip features such as UART and ADC

• Smallest microconroller is the ATtiny11 with 1k flash

ROM, no RAM and 6 I/O pins.

• Large such as the ATmega128 with 128k flash, 4KB

RAM, 53 I/O pins and lots of on-chip features.
 Basic families
AVRs are generally classified into following:
• tinyAVR –
– 0.5–16 KB program memory
– 6–32-pin package
– Limited peripheral set

• megaAVR – the ATmega series

– 4–256 KB program memory
– 28–100-pin package
– Extended instruction set (multiply instructions and
instructions for handling larger program memories)
– Extensive peripheral set
• XMEGA – the ATxmega series
– 16–384 KB program memory
– 44–64–100-pin package (A4, A3, A1)
– 32-pin package: XMEGA-E (XMEGA8E5)
– Extended performance features, such as DMA, cryptography support etc.
– Extensive peripheral set with ADCs

• Application-specific AVR
– megaAVRs with special features not found on the other members of the
AVR family, such as LCD controller, USB controller, advanced PWM, CAN,
etc.

• FPSLIC (AVR with FPGA)

– FPGA 5k to 40k gates
– SRAM for the AVR program code, unlike all other AVRs
– AVR core can run at up to 50 MHz
Let’s get familiar with the AVR part numbers

ATmega128

Atmel group
Flash
=128K

ATtiny44 AT90S4433

Atmel
Tiny Flash =4K Atmel Classic
Flash =4K
group group
The ATmega32 provides the following features:
• 32Kbytes of In-System Programmable Flash Program memory with Read-
While-Write capabilities
• 1024bytes EEPROM
• 2Kbyte SRAM
• 32 general purpose I/O lines
• 32 general purpose working registers
• A JTAG interface for Boundary scan
• On-chip Debugging support and programming
• Three flexible Timer/Counters with compare modes
• Internal and External Interrupts
• A serial programmable USART
• A byte oriented Two-wire Serial Interface
• An 8-channel, 10-bit ADC with optional differential input stage with
programmable gain
• A programmable Watchdog Timer with Internal Oscillator
• An SPI serial port
• Six software selectable power saving modes.
• The device is manufactured using Atmel’s high
density nonvolatile memory technology.

• The on chip ISP Flash allows the program memory to

be reprogrammed in-system through
– an SPI serial interface,
– by a conventional nonvolatile memory programmer,
– or by an On-chip Boot program running on the AVR core.

• The boot program can use any interface to download

the application program in the Application Flash
memory.
• Software in the Boot Flash section will continue to run
while the Application Flash section is updated,
providing true Read-While-Write operation.

• By combining an 8-bit RISC CPU with In-System

Self-Programmable Flash on a monolithic chip, the
Atmel ATmega32 is a powerful microcontroller that
provides a highly-flexible and cost-effective solution to
many embedded control applications.

• The Atmel AVR ATmega32 is supported with a full suite

of program and system development tools including: C
compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and
evaluation kits.
 Pin Configurations

Thin Profile Plastic Quad Flat Package /

Plastic Dual Inline Package Micro Lead Frame Package
ATMega32 Pin out & Descriptions

Port B Port A

Port C
Port D
• Digital IO is the most fundamental mode of connecting a MCU to
external world. The interface is done using a Port.
• A port is the point where internal data from MCU chip comes out
or external data goes in.
• They are present is form of Pins of the IC. Most of the PINs are
dedicated to I/O function and other pins are used for power supply,
clock source etc .
• ATMega32 ports are named PortA, PortB, PortC and PortD.

Port A
 General Purpose I/O Ports
• Four 8 Bit I/O Ports
– Port A, Port B, Port C & Port D
– Pins identified as PAx, PBx, PCx or PDx (x=0..7)

• Each pin can be configured as:

– Input with internal pull-up
– Input with no pull-up
– Output low
– Output high
Register Address of ATmega32 ports
Relations between the Registers and
the pins of AVR
• DDR : Data Direction Register
Value 0 : Port will act as Input
Value 1 : Port will act as Output

• PIN : Port INput

The I/O Port in AVR

Case 1 : To make a pin go high or low ( if it is an output pin)- Data Register PORTx

Port x
 Pull-up resistors
Pull-up resistors are used in electronic logic circuits to ensure
that inputs to logic systems settle at expected logic levels
if external devices are disconnected or high-impedance.

vcc
1 = Close
PORTx.n 0 = Open

pin n of
port x PINx.n

Outside the Inside the

AVR chip AVR chip

The Pull-up Resistor

Case 2 : To activate / Deactivate pull up resistors-Data Register PORTx

Port x
DDRx

0 1
PORTx

0 high impedance Out 0

1 pull-up Out 1
The PINx register gets the reading from the input pins of the MCU

Port x
 Programming
• Assign value 0x55 and 0xAA (alternatively after
specific delay) to the pin no. 33 to 40 of
Atmega32 (PDIP).

• Assign the value of Port A to Port C.

• Make the pull up resistor of port D active.

 I/O Bit Manipulation Programming
Single bit (bit-oriented) Instructions for AVR
The Lower 32 I/O Register
• SBI ioReg, bit_num
– e.g. : SBI PORTB, 2

– SBI Instruction Format

• SBIC ioReg, bit_num

• SBIS ioReg, bit_num

• Instruction Format
• e. g: Buzzer System
ATMega32 Architecture
Block Diagram of the AVR MCU Architecture
• In order to maximize performance and parallelism, the AVR
uses a Harvard architecture – with separate memories and
buses for program and data.

• Instructions in the program memory are executed with a

single level pipelining.

• While one instruction is being executed, the next instruction

is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle.

• The program memory is In-System Reprogrammable Flash

memory.
The Pipeline Vs. Non-pipeline Execution
Pipeline activity for both Fetch and Execute
 General Purpose Register File
• The fast-access Register File contains 32 × 8-bit
general purpose working registers with a single clock
cycle access time.

• This allows single-cycle Arithmetic Logic Unit (ALU)

operation.

• In a typical ALU operation, two operands are output

from the Register File, the operation is executed, and
the result is stored back in the Register File – in one
clock cycle.
• Six of the 32 registers can be used as three 16-bit indirect
address register pointers for Data Space addressing.

• The Register File is optimized for the Atmel®AVR® Enhanced

RISC instruction set.

• The following input/output schemes are supported by the

Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
AVR CPU General Purpose Working Registers
 The X-register, Y-register and Z-register
• The registers R26..R31 have some added functions to
their general purpose usage.

• These registers are 16-bit address pointers for indirect

addressing of the Data Space.

• The three indirect address registers X, Y, and Z are

defined.

• In the different addressing modes these address registers

have functions as fixed displacement, automatic
increment, and automatic decrement
The X-, Y-, and Z-registers
 The Arithmetic Logic Unit
• The ALU supports arithmetic and logic operations between registers or
between a constant and a register.

• Single register operations can also be executed in the ALU.

• After an arithmetic operation, the Status Register is updated to reflect

information about the result of the operation.

• Program flow is provided with conditional and unconditional jump and call
instructions, able to directly address the whole address space.

• Most AVR instructions have a single 16-bit word format.

• Every program memory address contains a 16- or 32-bit instruction.

AVR General Purpose Register and ALU
 Status Register
• The Status Register contains information about the result of
the most recently executed arithmetic instruction.

• This information can be used for altering program flow in

order to perform conditional operations.

• Status Register will in many cases remove the need for using
the dedicated compare instructions, resulting in faster and
more compact code.

• The Status Register is not automatically stored when entering

an interrupt routine and restored when returning from an
interrupt. This must be handled by software.
 The AVR Status Register – SREG

• Bit 7 – I: Global Interrupt Enable

– The Global Interrupt Enable bit must be set for the interrupts to be
enabled.
– The individual interrupt enable control is then performed in separate
control registers.
– If the Global Interrupt Enable Register is cleared, none of the interrupts are
enabled independent of the individual interrupt enable settings.
– The I-bit is cleared by hardware after an interrupt has occurred, and is set
by the RETI instruction to enable subsequent interrupts.
– The I-bit can also be set and cleared by the application with the SEI and CLI
instructions.
• Bit 6 – T: Bit Copy Storage
– The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the
T-bit as source or destination for the operated bit.
– A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in
the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

– The Half Carry Flag H indicates a half carry in some arithmetic
operations.
– Half Carry is useful in BCD arithmetic.

• Bit 4 – S: Sign Bit, S = N ⊕ V

– The S-bit is always an Exclusive-Or between the Negative Flag N and
the Two’s Complement Overflow Flag V.
• Bit 3 – V: Two’s Complement Overflow Flag
– The Two’s Complement Overflow Flag V supports two’s complement
arithmetic.

• Bit 2 – N: Negative Flag

– The Negative Flag N indicates a negative result in an arithmetic or logic
operation.

• Bit 1 – Z: Zero Flag

– The Zero Flag Z indicates a zero result in an arithmetic or logic
operation.

• Bit 0 – C: Carry Flag

– The Carry Flag C indicates a carry in an arithmetic or logic operation.
 AVR Status Register

• eg.1
;
;

• eg.2
;
;
• eg. 3

• eg. 4

• eg. 5
 Programming (Instructions)
• LDI Rd, K ; (LDI : Load Data Immediate)
– Rd represents any general purpose register between R16 to R31.
– K represents immediate 8 bit value.
– LDI instruction is not valid for R0 to R15.

• ADD Rd, Rr ; Rd = Rd + Rs

• IN Rd, A ; (IN from I/O location)

– Rd represents general purpose register
– A represents I/O register

• OUT A, Rr ; (OUT to I/O location)

– Rd represents general purpose register
– A represents I/O register
• LDS Rd, K ; (LoaD data from data Space)
– K is the data memory address between 0x0000 to
0xFFFF
– 0 ≤ d ≤ 31
– The location in data memory can be any part of
the data space; it can be one of the I/O registers,
a location in the internal SRAM, or a GPR.
• STS K, Rr ; (STore direct to data Space)
– K is an address between 0x0000 to 0xFFFF;
– The location can be in any part of the data memory
space; it can be one of the I/O registers, a location in
the SRAM, or a GPR.
– eg : STS 0x01, R10;
• R1 <= R10

• WAP to assign a value 0x55 on PORTA register.

• WAP to perform the addition between the contents

available on port A and port C and display the result on pin
no. 01-08 (ATmega32) (DIP packaging).
The Lower 32 I/O Register
eg :

Answer :
 IN Vs. LDS
Advantages
• IN instruction faster than LDS. The IN instruction lasts
1 machine cycle, whereas LDS lasts 2 machine cycle.
• IN is a 2-byte instruction whereas LDS is a 4-byte
instruction.

Disadvantage
• IN instruction are applicable to only the standard IO
memory whereas we can access all parts of data
memory using LDS instruction.
 Program Flash memory & SRAM

• Program Flash memory space is divided in two

sections,
– The Boot program section
– The Application Program section

• Both sections have dedicated Lock bits for write and

read/write protection.
• The Stack is effectively allocated in the general data
SRAM, and consequently the Stack size is only limited by
the total SRAM size and the usage of the SRAM.

• All user programs must initialize the SP in the reset

routine (before subroutines or interrupts are executed).

• The Stack Pointer (SP) register is read/write accessible in

the I/O space.

• The data SRAM can easily be accessed through the five

different addressing modes supported in the AVR
architecture.
 I/O Memory Space
• A flexible interrupt module has its control registers in the I/O space
with an additional global interrupt enable bit in the Status Register.

• All interrupts have a separate interrupt vector in the interrupt vector

table.

• The interrupts have priority in accordance with their interrupt vector

position. The lower the interrupt vector address, the higher the
priority.

• The I/O memory space contains 64 addresses for CPU peripheral

functions as Control Registers, SPI, and other I/O functions.

• The I/O Memory can be accessed directly, or as the Data Space

locations following those of the Register File, $20 - $5F.
 Stack Pointer
• The Stack is mainly used for storing temporary data, for
storing local variables and for storing return addresses after
interrupts and subroutine calls.

• The Stack Pointer Register always points to the top of the

Stack.

• Note that the Stack is implemented as growing from higher

memory locations to lower memory locations.

• This implies that a Stack PUSH command decreases the

Stack Pointer.
• The Stack Pointer points to the data SRAM Stack area
where the Subroutine and Interrupt Stacks are located.

• This Stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or
interrupts are enabled.

• The Stack Pointer must be set to point above $60.

• The Stack Pointer is decremented by one when data is pushed onto
the Stack with the PUSH instruction, and it is decremented by two
when the return address is pushed onto the Stack with subroutine
call or interrupt.

• The Stack Pointer is incremented by one when data is popped from

the Stack with the POP instruction, and it is incremented by two
when data is popped from the Stack with return from subroutine RET
or return from interrupt RETI.

• The AVR Stack Pointer is implemented as two 8-bit registers in the I/O
space.The number of bits actually used is implementation dependent.

• Note that the data space in some implementations of the AVR

architecture is so small that only SPL is needed. In this case, the SPH
Register will not be present.
ATMega32 Programmer Model: Registers

20112012-I Module 2/74

 ATmega32 Memories
• The AVR architecture has two main memory
spaces :
– The Data Memory space
– The Program Memory space

• In addition, the ATmega32 features an

EEPROM Memory for data storage.
In-System Reprogrammable Flash Program Memory
• The ATmega32 contains 32 Kbytes On-chip In-System Reprogrammable
Flash memory for program storage.

• Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
16K × 16.

• For software security, the Flash Program memory space is divided into
two sections,
– Boot Program section
– Application Program section.

• The Flash memory has an endurance of at least 10,000 write/erase

cycles.

• The ATmega32 Program Counter (PC) is 14 bits wide, thus

addressing the 16K program memory locations.
Flash Program Memory Map
SRAM Data Memory

Data Memory Map

• For Atmega32, the 2144 Data Memory locations address
– The Register File
– The I/O Memory
– The internal data SRAM.

• The first 96 locations address the Register File and I/O Memory,
and the next 2048 locations address the internal data SRAM.
 EEPROM Data Memory
• The ATmega32 contains 1024 bytes of data EEPROM memory.

• It is organized as a separate data space, in which single bytes can be

read and written.

• The EEPROM has an endurance of at least 100,000 write/erase cycles.

• EEPROM does not lose its data when power is OFF, whereas SRAM
does.

• So, the EEPROM is used for storing data that should rarely be
changed and should not be lost when the power is OFF ; whereas
the SRAM is used for storing data and parameters that are changed
frequently.
 Stack and Stack Pointer
• The CPU needs Stack storage area because there are only limited no. of
registers.

• Two registers from I/O memory space are used to initialize stack pointer.

Stack Pointer

• Initializing Stack Pointer :

– When AVR is powered up , the SP register contains the value 0, which is the
address of R0.
– Therefore, we must initialize the SP at the beginning of program.
 Pushing onto the stack
• The Stack Pointer (SP) points towards the top of the
stack.

• As we push data onto the stack, the data are saved

where SP points to, and the SP is decremented by one.

• PUSH Rr;
– Rr can be any general purpose registers (R0 - R31)

• PUSH R10;
– Store R10 onto the stack and decrement SP.
 Popping from the Stack
• Popping the contents of the stack back into the given register is
the opposite process of pushing.

• When the POP instruction is executed, the SP is incremented and

the top location of the stack is copied back to the register.

• That means the stack is LIFO memory.

• POP Rd;
– Rd can be any general purpose registers (R0 - R31)

• eg : POP R10;
– Increment SP, and then load top of the stack to R16.
• eg : 0x 08 After Execution :
0x 5F
 CALL instruction and the role of Stack
• When the subroutine is called, the processor first
saves the address of the instruction just below the
CALL instruction (contents of PC) on the stack, and
then transfers control to that subroutine.

• This is how the CPU knows where to resume when it

returns from the called subroutine.

• The higher byte of PC is pushed onto the stack first,

and then the lower byte is pushed.
 RET instruction and the role of Sack
• RET instruction is executed at the end of subroutine.

• CALL instruction PUSH the address of next instruction

to be executed (i.e. contents of PC) from main program
onto the stack whereas RET instruction POP it after the
execution of subroutine.

• After execution of RET instruction, the top location of

the stack is copied back to the PC and the SP is
incremented.
• Analyze the stack for CALL instruction.
Flash Memory Address
0x 08
0x 5F

• Ans:

PC = 0x0006 PC = 0x0300 PC = 0x0008 PC = 0x0300 PC = 0x000C

• Write a program to count up from 0x00 to 0xFF and send count to
PORTB register. Use one CALL subroutine for sending the data to PORTB
register and another one for time delay. Put a time delay between each
issuing of data to PORTB register.
• Solution : Flash Memory Address
 AVR Time Delay
• Instruction cycle Time for the AVR
– CPU takes certain amount of time to execute instruction, this time is
referred to as Machine cycle.

– Because all the instructions in the AVR are either 2-byte or 4-byte, most
instruction takes no more than one or two machine cycle to execute.

– In the AVR family, the length of machine cycle depends on the frequency
of the oscillator connected to the AVR system.

– In the AVR, one machine cycle consists of one oscillator period, which
means that with each oscillator clock, one machine cycle passes.

– Therefore, to calculate the machine cycle for the AVR, we take the
inverse of the crystal frequency.
 eg. : Find the size of delay of the code mention below if

the crystal frequency = 10 MHz.

Ans : Time Delay = [1 + ((1+1+1+2) * 255 ) -1 + 4] x 0.1 us

= 127.9 us
eg. : For an instruction cycle of 1 us, find the
delay in the following subroutine.

Ans : 250,604 us
• Write a program to toggle all the bits of I/O
register PORTB every 1 sec. Assume that crystal
frequency is 8 MHz.
 Register and Direct Addressing Mode
• The various ways of accessing data which are available in memory,
register or as an immediate value, are called addressing mode.

• The various addressing modes of a microcontroller are

determined when it designed, and therefore cannot be changed
by the programmer.

• The AVR addressing modes are categorized into following groups :

• Single Register (Immediate)
• Two Register
• Direct
• Register Indirect
• Flash Direct
• Flash Indirect
 Single Register (Immediate) Addressing Mode

• In this addressing mode, the operand is a register.

• eg. :
Single Register (Immediate) Addressing Mode
Cont…
 Two Register Addressing Mode
• This addressing mode involves the use of two
registers to hold the data to be manipulated.

• eg. :
Two Register Addressing Mode
Cont…
 Direct Addressing Mode
• The entire memory can be accessed using direct
addressing mode.

• In this direct mode, operand data is in a RAM memory

location whose address is known, and this address is
given as a part of the instruction.

• Contrast this with immediate addressing in which the

operand data itself is provided with the instruction.
• It must be noted that data memory does not support
immediate addressing mode.

• In other words, to move data into internal RAM or to I/O

registers, we must first move it to a GPR (R16-R31), and
then move it from the GPR to the data memory space
using the STS instruction.

• eg . :
Direct Addressing Mode
Cont…
 I/O Direct Addressing Mode
• The I/O direct addressing mode can address only
the standard I/O registers.

• eg. : IN R16, PINB;

OUT PORTB, R17;

• WAP to send a value 0x0A on Port C. Include

1. the register name
2. the I/O address
3. the data memory address
Some ATmega32 I/O register Address
I/O Direct Addressing Mode
Cont…
 Register Indirect Addressing Mode
• In this mode, a register is used as a pointer to data memory
location.

• In the AVR, 3 registers are used for this purpose :

– Register X (R27 : R26)
– Register Y (R29 : R28)
– Register Z (R31 : R30)
• Syntax :
– LD R21, X ; (Load into R21 from the location pointed to by X)
– ST Y, R25 ; (Store into the location pointed by Y from R25)

• What will be the output of following program.

– LDI XL , 0x 1F;
LDI XH, 0x 01;
The content of memory location 0x011F get
LD R24, X;
copied to GPR R24.

– LDI YL, 0x 20;

LDI YH, 0x 01;
The content of GPR R24 get copied to
ST Y, R24;
memory location 0x0120.
After execution of above two set of instructions, the content of
memory location 0x011F get copied to memory location 0x0120.
Register Indirect Addressing Mode
Cont…
Flash Direct and Indirect Addressing Mode
 Logic Operations in C
• Shift operation
• Bitwise AND operation
• Bitwise OR operation