Electromigration and IR

By
Harish
 What is Electromigration?


Gradual displacement of metal atoms in a semiconductor

when the current density is high enough to cause the drift of
metal ions in the direction of the electron flow

Depends on the magnitude of forces that tend to hold the ions
in place

nature of the conductor, crystal size and interface

current density, temperature and mechanical stresses
Failure Mechanism


There are two different EM failure mechanisms that occur
due to asymmetry in the ion flow.

A void where the outgoing ion flux exceeds the incoming
ion flux: open circuit
 Failure Mechanism


A hillock where the incoming ion flux exceeds the
outgoing ion flux: short circuit
Electromigration Dependency on Physical
Effects


Wire Width

By increasing the wire width, current density is reduced and
susceptibility to EM is reduced


Wire Length

a lower limit for the length of interconnect that will be subjected
to the effects of electron migration
 Electromigration Dependency on Physical
Effects


Impact of Physical Layout

Interconnect layout has an impact on electron migration and
current density

90° corners and rapid wire width reduction should be avoided

current crowding and rapid increase in current density
exacerbate EM
 IR Drop

 Every chip will have IR Drop


Designers need to understand impact of IR drop on
functionality

Functional (Logic level) change due to noise margin
reduction

10% IR drop may increase delay up to 8%

Timing failures due to circuit slow down or speed-up
IR Drop
 For EM :
 Increasing the metal width
 Metal slotting
 Metal stacking
 Parallel routing
 More vias.

 For IR drop :
 Going for higher metal (wider width)
 Parallel routing
Tools for EM IR checks

 Samsung -- Totem tool 10nm for EMIR

 EM will be 2 types 1) signal EM 2) power EM
 In every company they will follow some percentage levels for
EM and IR.
 While running in tool after simulation it will highlight that
particular area where we are getting violations.
 For example in some particular company they will allow up
to 100% for EMIR if we are getting more that percentage(i.e.
required) we have to fix those nets.
 Intel -- Genesys 10nm 14nm.
 For EM we will use RV calculator and for verification we
will go for RV CHECK

 SONY -- Red hawk (schematic designer will run after

submitting the layout )

 Synopsys -- Custom sim

 Cadence -- Volcus
 Mentor graphics -- Apache totem
Thank you
questions

 Extension file ?
 Metal slotting?
 Static and dynamic drop?