The 8051 Microcontroller architecture

Three criteria in Choosing a Microcontroller

1. meeting the computing needs of the task efficiently and cost

effectively
• speed, the amount of ROM and RAM, the number of I/O
ports and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
2. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support
3. wide availability and reliable sources of the microcontrollers.
The 8051 microcontroller

• a Harvard architecture (separate instruction/data memories)

• single chip microcontroller (µC)
• developed by Intel in 1980 for use in embedded systems.
 8051 microcontroller
• It is an 8-bit microcontroller.
• It is built with 40 pins DIP (dual inline package), 4kb of
ROM storage and 128 bytes of RAM storage,
• 2 16-bit timers.
• It consists of are four parallel 8-bit ports, which are
programmable as well as addressable as per the
requirement.
• An on-chip crystal oscillator is integrated in the
microcontroller having crystal frequency of 12 MHz.
 Block Diagram
External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
RAM Timer 0 Inputs
code

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data
 Comparison of the 8051 Family Members

Feature 8051 8052 8031

ROM (program space in bytes) 4K 8K 0K
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6
Pin Description of the 8051

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 8051 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6
(8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

• Pins 1 to 8 − These pins are known
as Port 1. This port doesn’t serve P1.0 1 40 Vcc
P0.0(AD0)
P1.1 2 39
any other functions. It is internally P1.2 3 38 P0.1(AD1)

pulled up, bi-directional I/O port. P1.3

P1.4
4
5
8051 37
36
P0.2(AD2)
P0.3(AD3)
(8031)
• Pin 9 − It is a RESET pin, which is P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
used to reset the microcontroller P1.7 8 33 P0.6(AD6)

to its initial values. RST

(RXD)P3.0
9 32 P0.7(AD7)
10 31 EA/VPP
• Pins 10 to 17 − These pins are (TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
known as Port 3. This port serves (INT1)P3.3 13 28 P2.7(A15)

some functions like interrupts, (T0)P3.4

(T1)P3.5
14 27 P2.6(A14)
P2.5(A13)
15 26
timer input, control signals, serial (WR)P3.6 16 25 P2.4(A12)

communication signals RxD and (RD)P3.7

XTAL2
17
18
24
23
P2.3(A11)
P2.2(A10)
TxD, etc. XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
• Pins 18 & 19 − These pins are used
for interfacing an external crystal P1.0 1 40 Vcc
P0.0(AD0)
P1.1 2 39
to get the system clock. P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
• Pin 20 − This pin provides the P1.4 5
8051
36 P0.3(AD3)
(8031)
power supply to the circuit. P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
• Pins 21 to 28 − These pins are P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
known as Port 2. It serves as I/O (RXD)P3.0 10 31 EA/VPP
port. Higher order address bus (TXD)P3.1
(INT0)P3.2
11 30 ALE/PROG
12 29 PSEN
signals are also multiplexed using (INT1)P3.3 13 28 P2.7(A15)

this port. (T0)P3.4

(T1)P3.5
14 27 P2.6(A14)
P2.5(A13)
15 26
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
• Pin 29 − This is PSEN pin which stands
P1.0 1 40 Vcc
for Program Store Enable. It is used to P1.1 2 39 P0.0(AD0)
read a signal from the external P1.2 3 38 P0.1(AD1)
program memory. P1.3 4 8051 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
• Pin 30 − This is EA pin which stands for P1.5 6
(8031) 35 P0.4(AD4)
External Access input. It is used to P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
enable/disable the external memory RST P0.7(AD7)
9 32
interfacing. (RXD)P3.0 10 31 EA/VPP

• Pin 31 − This is ALE pin which stands (TXD)P3.1 11 30 ALE/PROG

(INT0)P3.2 12 29 PSEN
for Address Latch Enable. It is used to (INT1)P3.3 13 28 P2.7(A15)
demultiplex the address-data signal of (T0)P3.4 14 27 P2.6(A14)
port. (T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
• Pins 32 to 39 − These pins are known (RD)P3.7 17 24 P2.3(A11)
as Port 0. It serves as I/O port. Lower XTAL2 18 23 P2.2(A10)
P2.1(A9)
order address and data bus signals are XTAL1 GND
19
20
22
21 P2.0(A8)
multiplexed using this port.
• Pin 40 − This pin is used to provide
power supply to the circuit.
RESET Value of Some 8051 Registers:

Register Reset Value

PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero.

Pins of I/O Port

• The 8051 has four I/O ports

• Port 0 （ pins 32-39 ）： P0 （ P0.0 ～ P0.7 ）
• Port 1 （ pins 1-8 ） ： P1 （ P1.0 ～ P1.7 ）
• Port 2 （ pins 21-28 ）： P2 （ P2.0 ～ P2.7 ）
• Port 3 （ pins 10-17 ）： P3 （ P3.0 ～ P3.7 ）
• Each port has 8 pins.
• Named P0.X （ X=0,1,...,7 ） , P1.X, P2.X, P3.X
• Ex ： P0.0 is the bit 0 （ LSB ） of P0
• Ex ： P0.7 is the bit 7 （ MSB ） of P0
• These 8 bits form a byte.
• Each port can be used as input or output (bi-direction).

 Registers
• Types of Registers
• The 8051 microcontroller contains mainly two types of
registers:
• General purpose registers (Byte addressable registers)
• Special function registers (Bit addressable registers)
• The 8051 microcontroller consists of 256 bytes of RAM memory,
which is divided into two ways,
such as 128 bytes for general purpose
and 128 bytes for special function registers (SFR) memory.
• The memory which is used for general purpose is called as RAM
memory,
and
• the memory used for SFR contains all the peripheral related
registers like Accumulator, ‘B’ register, Timers or Counters, and
interrupt related registers.
 General Purpose Registers

The general purpose memory is called as the RAM

memory of the 8051 microcontroller, which is divided
into 3 areas such as
banks,
bit-addressable area, and
scratch-pad area.
The banks contain different general purpose registers
such as R0-R7, and all such registers are byte-
addressable
Banks registers that store or remove only 1-byte
and Registers
of data.
The B0, B1, B2, and B3 stand for banks and each bank contains
eight general purpose registers ranging from ‘R0’ to ‘R7’.
All these registers are byte-addressable registers.

Data transfer between general purpose registers to general

purpose registers is not possible.

These banks are selected by the Program Status Word (PSW)

register.
Registers

• The Accumulator
• The "R" registers
• The "B" Register
• The Data Pointer (DPTR)
• The Program Counter (PC)
• The Stack Pointer (SP)
• The Accumulator
• The Accumulator, as it’s name suggests, is used as a register to
accumulate the results of a large number of instructions. It can
hold an 8-bit (1-byte) value.

• The "R" registers

• The "R" registers are a set of eight registers that are named R0,
R1, etc. up to and including R7.
• These registers are used as auxillary registers in many
operations. To continue with the above example, perhaps you
are adding 10 and 20. The original number 10 may be stored in
the Accumulator whereas the value 20 may be stored in, say,
register R4. To process the addition you would execute the
command:
• ADD A,R4
• The "B" Register
• The "B" register is very similar to the Accumulator in
the sense that it may hold an 8-bit (1-byte) value.
• The "B" register is only used by two 8051 instructions:
MUL AB and DIV AB. Thus, if you want to quickly and
easily multiply or divide A by another number, you
may store the other number in "B" and make use of
these two instructions.
• Aside from the MUL and DIV instructions, the "B"
register is often used as yet another temporary
storage register.
• The Data Pointer (DPTR)

• The Data Pointer (DPTR) is the 8051’s only user-accessable 16-

bit (2-byte) register. The Accumulator, "R" registers, and "B"
register are all 1-byte values.

• DPTR, is used to point to data. It is used by a number of

commands which allow the 8051 to access external memory.
When the 8051 accesses external memory it will access
external memory at the address indicated by DPTR.
• The Program Counter (PC)

• The Program Counter (PC) is a 2-byte address which tells the

8051 where the next instruction to execute is found in
memory. When the 8051 is initialized PC always starts at 0000h
and is incremented each time an instruction is executed. It is
important to note that PC isn’t always incremented by one.
Since some instructions require 2 or 3 bytes the PC will be
incremented by 2 or 3 in these cases.

• It is also interesting to note that while you may change the

value of PC (by executing a jump instruction, etc.)
• The Stack Pointer (SP)
• The Stack Pointer, like all registers except DPTR and
PC, may hold an 8-bit (1-byte) value. The Stack Pointer
is used to indicate where the next value to be
removed from the stack should be taken from.
• When you push a value onto the stack, the 8051 first
increments the value of SP and then stores the value
at the resulting memory location.
• When you pop a value off the stack, the 8051 returns
the value from the memory location indicated by SP,
and then decrements the value of SP.
SFR Addr Function
ess
DPH 83 Data pointer registers (High). Only byte
addressing possible.
DPL 82 Data pointer register (Low). Only byte
addressing possible.
IP B8 Interrupt priority. Both bit addressing and
byte addressing possible.
IE A8 Interrupt enable. Both bit addressing and
byte addressing possible.
SBUF 99 Serial Input/Output buffer. Only byte
addressing is possible.
SCO 98 Serial communication control. Both bit
N addressing and byte addressing possible.
TCO 88 Timer control. Both bit addressing and byte
N addressing possible.
TH0 8C Timer 0 counter (High). Only byte
SFR Ad Function
dr
es
s
TH0 8C Timer 0 counter (High). Only
byte addressing is possible.
TL0 8A Timer 0 counter (Low). Only
byte addressing is possible.
TH1 8D Timer 1 counter (High). Only
byte addressing is possible.
Power Management Register (PCON)

• this register is used for efficient power management of 8051 micro

controller. Commonly referred to as PCON register, this is a
dedicated SFR for power management alone
Processor Status Word (PSW)

• This register reflects the status of the operation that is being carried
out in the processor. 
Memory Map (RAM)
CPU timing

• Most 8051 instructions are executed in one cycle.

• MUL (multiply) and DIV (divide) are the only
• instructions that take more than two cycles to complete
(four cycles)
• Normally two code bytes are fetched from the program
memory during every machine cycle.
• The only exception to this is when a MOVX instruction is
executed. MOVX is a one-byte, 2-cycle instruction that
accesses external data memory.
• During a MOVX, the two fetches in the second cycle are
skipped while the external data memory is being addressed
and strobed.
8051 machine cycle
Example :

Find the machine cycle for

(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.

Solution:

(a) 11.0592 MHz / 12 = 921.6 kHz;

machine cycle = 1 / 921.6 kHz = 1.085 s
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 s


Edsim51 emulator diagram
KitCON-515 schematic
Timers

• 8051 has two 16-bit on-chip timers that can be used for timing
durations or for counting external events
• The high byte for timer 1 (TH1) is at address 8DH while the low byte
(TL1) is at 8BH
• The high byte for timer 0 (TH0) is at 8CH while the low byte (TL0) is at
8AH.
• Timer Mode Register (TMOD) is at address 88H
 Timer Mode Register
• Bit 7: Gate bit; when set, timer only runs while \INT high.
(T0)
• Bit 6: Counter/timer select bit; when set timer is an event
counter when cleared timer is an interval timer (T0)
• Bit 5: Mode bit 1 (T0)
• Bit 4: Mode bit 0 (T0)
• Bit 3: Gate bit; when set, timer only runs while \INT high.
(T1)
• Bit 2: Counter/timer select bit; when set timer is an event
counter when cleared timer is an interval timer (T1)
• Bit 1: Mode bit 1 (T1)
• Bit 0: Mode bit 0 (T1)
Timer Modes

• M1-M0: 00 (Mode 0) – 13-bit mode (not commonly used)

• M1-M0: 01 (Mode 1) - 16-bit timer mode
• M1-M0: 10 (Mode 2) - 8-bit auto-reload mode
• M1-M0: 11 (Mode 3) – Split timer mode
8051 Interrupt Vector Table
The Stack and Stack Pointer

• The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-
byte) value.
• The Stack Pointer is used to indicate where the next value to be removed from
the stack should be taken from.
• When you push a value onto the stack, the 8051 first increments the value of SP
and then stores the value at the resulting memory location.
• When you pop a value off the stack, the 8051 returns the value from the
memory location indicated by SP, and then decrements the value of SP.
• This order of operation is important. When the 8051 is initialized SP will be
initialized to 07h. If you immediately push a value onto the stack, the value will
be stored in Internal RAM address 08h. This makes sense taking into account
what was mentioned two paragraphs above: First the 8051 will increment the
value of SP (from 07h to 08h) and then will store the pushed value at that
memory address (08h).
• SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL,
RET, and RETI. It is also used intrinsically whenever an interrupt is triggered