REVERSIBLE LOGIC GATES AND

ITS PERFORMANCES

PROJECT GUIDE SUBMITTED BY

SHAIK SOHEL PASHA G.ANANYA (16W91A0476)
L.SRIKER (16W91A0489)
T.TEJA PAVAN KALYAN (16W91A04C1)
K.DHARMA TEJA (16W91A0484)
 ABSTRACT
 Heat is an important issue in VLSI circuits since the reversible
logic gives zero amount of heat dissipation so, it plays an
important role in nanotechnology.
 So we are using reversible logic technology for decreasing the
energy dispersion, heatwave dissipation, increasing rapidness
etc.
 It is used to maximize the speed and reduce energy
consumption. There are different types of reversible logic
gates like fredkin, peres, Double Feynman, Feynman
,reversible HNG and toffoli gate etc. and in this project we
have used peres gate to design the adder and multiplier circuits
 INTRODUCTION TO PROJECT
 In reversible logic, the number
of inputs are equal to number the
outputs of the gates in order to
have a one-to-one mapping.
 This generates a unique set of
output vector for each set of
input vector.
 This prevents the loss of
information which causes power
dissipation.
 In reversible logic fan-out is not
possible and feedback or loops
are not allowed
 EXISTING PROJECT
 The existing project is on 1-bit adder and subtractor by using
reversible logic gates and he has used pass transistor and
cmos logic
 Since it is designed for only one bit operation it takes more
time to perform the operation
 So we are proposing the project of 8-bit adder and 3-bit
multiplier
 PROPOSED PROJECT
We are designing an 8-bit adder and 3-bit multiplier
circuits in this project
We would be taking different full adder and half adder
circuits to design the adder and multiplier circuit
In this we would be using Xilinx software to verify the
code which we have written is correct or not
Firstly we are taking a reversible logic gate
In this we are taking reversible peres gate since by
using the reversible peres gate we could be getting the
exact output for the half adder circuit
 For that we will be writing a verilog code for this gate
and will be checking whether we are getting the exact
output of that gate by simulation
 Then by using that peres gate we would be writing a
verilog code for designing a half adder circuit
 After that we would be taking two half adder circuits to
design a full adder circuit
 We would be checking the simulation and rtl circuit
whether we are getting the full adder output correctly or
not
 By using the 8 full adders we would be designing an 8-bit
adder circuit
 We would be giving two 8-bit inputs and we would be
adding both the inputs using the verilog code and will
simulate that code
 For designing a 3-bit multiplier circuit we will be
using 10 AND gates and 3 half adders and 3 full
adder circuits
 We will be writing a verilog code by using the above
mentioned gates and adders and we will do
stimulation to check whether we are getting the
output of 3-bit multiplier
 If we get the exact output we will be doing the RTL
analysis to get circuit design of 3-bit multiplier
 The outputs of this project are shown below
 OUTPUT
• 8-bit Adder
RTL output
Simulation output
• 3-bit Multiplier
RTL output
Simulation output
 CONCLUSION
Use of the reversible logic gates are increasing
day by day but the scientists are still continue with
their work on this to further more decreasing
environmental decay growth . So mostly we can use
this for the power consumption. In this we explained
the types of the logic gates and its uses and how we
can implement on these logic gates. In this have
shown the adder circuit of 8-bit and multiplier 3-bit
and after use of reversible logic gates definitely its
energy consumption and delays are less than its actual
circuit design.
 Future Scope
In future we can increase the bit length such that
we would be increasing the speed and decrease the
size of the circuit
THANK YOU