Stimulus Generation And

Randomization
 SV Datatypes
4 Valued Datatype:
logic, Integer and reg are 4 value datatype which can have value of X,Z,0,1
with default values as X.
logic – 1bit
Integer – 32 bit.
2 Valued Datatype:
Bit,byte ,int are 2 Valued datatype which can have value of 0,1 with
default value as 0.
int – 32 bit.
Shortint – 16 bit.
longint – 64 bit.
byte – 8 bit .
 System Verilog Classes
• Classes in SV has by default has all it’s function and data
member as Public ( They can be accessed directly through
object).
• If we want to make it private to that class then we use private
keyword before member name.
CONSTRUCTOR: Initialization of any variable can be done in
constructor.
EX: function new;
Addr = 16’h ffff;
Data_in = 0;
endfunction
 Inheritance in SV
• Like in any OOP language SV supports inheritance property.
• We can write common functionality or data in base classes which can
be utilised by derived class.
• Example:
class input1 ;
bit[7:0] trans1;
class input2 extends input1;
bit [7:0] trans2;
Both trans1 and trans2 is part of class input2 .
Input2 in2;
In2 = new();
In2. trans1 = 8’hf0f0;
 Abstract Class
• Virtual keyword can be used if we want class to be
abstract .
• We Can’t create object of the abstract classes.
• Library classes use abstract class feature.
• Example:
virtual class seq1;
// data and function declaration.
• Any class extended from abstract class becomes by
default abstract.
 Pure Virtual function
• Pure virtual function is abstract function with empty definition.
• If Base class has any pure virtual function then any of the derived
class has to implement it’s body otherwise derived class will
become abstract class.
Example:
Class trans_base;
Pure virtual function trans_base();
Class trans_derived extends trans_base;
function trans_base;
//Definition of function
Endfunction
 Stimulus Generation
class myclass
rand logic [7:0] in1;
rand logic[7:0] in2;
endclass
myclass m1;
int k;
Initial
begin
m1 =new;

For(int p=0;p<100;p++)
begin
k=m1.randomize;
$dispaly(“in1=%b in2=%b”,m1.in1,m1.in2);
end
end
 Constraint
class myclass
rand logic [7:0] in1;
rand logic[7:0] in2;
Constraint con1{ in1 < 8’d100 ;}
Endclass
myclass m1;
int k;
Initial
begin
m1 =new;
k = m1.randomize;
For(int p=0;p<100;p++)
begin
k=m1.randomize;
$dispaly(“in1=%b in2=%b”,m1.in1,m1.in2);
end
end
 Few Examples of Constraint
• 1) even numbers => constraint con1 { in1[0] ==
1’b0;}
• 2) multiple constraint => constraint con2
{ in1[0] ==1’b1 ; in2 < 8’d50;}
• 3) conflict =>
• 4) multiple of 5 => constraint con3 {in1
inside{8’d0,8’d5,8’d10,8’d15,8’d20,8’d25};}
 Few examples of constraint
• 5) range => constraint con5 { in1 inside{8’d5,
[8’d15:8’d20],8’d30,8’d40};}
• 6) not want to generate => constraint con6{ !(in1
inside{8’d0,8’d5,8’d10,8’d15,8’d20,8’d25});}
• 7) constraint con7 {
if(in1[0] == 1’b0)
in2! = 0;}
8) Constraint 8 { (in1[0] == 1’b0) -> in2! =0;}
 Few examples of Constraint
• 9) more frequently => constraint con9{in1 dist
{8’d2:=60,8’d4:=20,8’d8:=20};}
• 10) constraint con10{in1 dist{8’d2:=70,
[8’d6:8’d9]:=20,8’d10:=10};}
 Active-deActive Constraints
• 1) k=m1.randomize;
• 2) m1.constraint_mode(0)=> suppress all
constraint
• 3) m1.con1.constraint_mode(1);
• 4) m1.con2.constraint_mode(0);
 Randomize function calling
• 1) k=p1.randomize with { in1<8’d100;}
• 2)k=p1.randomize(in1);
• 3) k=p1.randomize(in1,in2);
 rand c && array
• 1) rand c bit[2:0] ctr;
constraint con1 { in2 inside{3’d2,3’d5,3’d7};}
2) rand bit [7:0] data_in;
constraint con12{ foreach(data_in[p]) (p>0)
&& (p<7) -> {data_in[p+1],data_in[p],data_in[p-
1] != 3’b0101;};}