Memory Segmentation, Generating Memory Address: Mustafa Shakir

‫مادة الفصل الثاني‬
Memory segmentation,
generating memory
address
LE CT URE R. RIYADH B ASSIL
MUSTAFA SHAKIR
Memory segmentation, generating memory address
A Reloadable Program: Is one that can be placed into any area of memory and executed
without change.
A Relocated Data: Are data that can be placed in any area of memory and used without
any change to the program.
Q) Why Segment and Offset Addressing Scheme allows programs and data to be
relocated without changing anything in the programs or data.
The memory segment can be moved to any place in the memory system without
changing any of the offset address. This is accomplished by moving the entire program,
as a block, to a new area and then changing only the contents of the segment register.
A typical Assembly language program consist of at least three segments:
1. A code segment
2. A data segment
3. A stack segment
Physical Address Is the 20-bit address that is actually put on the address pins of the
8086 CPU and decoded by the memory interfacing circuitry.
 This address can have a range of 00000H to FFFFFH for the 8086. It is an actual
physical location in RAM or ROM within the (1 megabyte) memory range.
Offset Address Is a location within 64K-byte segment range. The offset address can
range from 0000H to FFFFH.
Logical Address Consists of a segment value and an offset address.

The Code segment:

logical address of an instruction always consists of a CS (code segment)
and an IP (instruction pointer), shown in CS:IP format.
1.Start with CS.
2.Shift left CS.
3.Add IP.
Example 1:
If CS = 24F6H and IP = 634AH, show: and Calculate
(a)The logical address (c) The physical address
(b)The offset address (d) The lower range
Solution: (e) The upper range of the code segment
(a)24F6:634A (c) PA= (segment value * 10 + offset) = (24F60 + 634A) = 2B2AA

(b) 634A (d) Lower Range = (segment value * 10 + 0000) = (24F60 + 0000) = 24F60
(e) Upper Range = (segment value * 10 + FFFF) = (24F60 + FFFF) = 34F5F
The three columns show the logical address of CS:IP, the machine code stored at that
address and the corresponding Assembly language code.
Example 2:
If DS = 7EA2H and the offset is 438EH,
(a) Calculate the physical address. (b) Calculate the lower range.
(c) Calculate the upper range of the data segment. (d) Show the logical address.
Solution:
(a) PA= (segment value*10+offset) = (7EA20+438E) = 83DAE
(b) Lower Range = (segment value*10 + 0000) = (7EA20+0000) = 7EA20
(c) Upper Range = (segment value * 10 + FFFF) = (7EA20 + FFFF) = 8FA1F
(d) 7EA2:438E
Example 3:Assume that the DS register contains the value is 578CH. To access a given
byte of data at physical memory location 67F66H, does the data segment cover the range
where the data is located? If not, what changes need to be made?
Solution:
Lower Range = (segment value * 10 + 0000) = (578C + 0000) = 578C0
Upper Range = (segment value * 10 + FFFF) = (578C0 + FFFF) = 678BF
No, since the range is 578C0 to 678BF, location 67F66 is not included in this range. To
access that byte, DS must be changed so that its range will include that byte.
Little Endian Convention:

Previous examples used 8-bit or 1-byte data. In this case the bytes are stored one
after another in memory. What happens when 16-bit data is used?
MOV AX, 35F3H
MOV [1500H], AX
In cases like this, the low byte goes to the low memory location and the high bytes
goes to the high memory address.
DS:1500 = F3H DS:1501 = 35H

Example 4:
Assume memory locations with the following contents: DS:6826 = 48
and DS:6827 = 22. Show the contents of register BX in the instruction
MOV BX, [6826H]
Solution:
DS:6826 = 48
DS:6827 = 22
A single physical address can belong to many different logical addresses. E. g.
Logical address (hex) Physical address (hex)

1000:5020 15020
1500:0020 15020
1502:0000 15020
1400:1020 15020
1302:2000 15020
Hardware Organization of Memory
Address Space, Data Organization (aligned
& misaligned word, double word)
LECTURER. RIYADH BASSIL

Hardware Organization of Memory Address
Space, Data Organization (aligned & misaligned
word, double word)
Q) Explain the logical and physical organizations memory address space of the
8086-based microcomputers.
 Logically, memory is implemented as a single 1M × 8 memory chunk. The byte-
wide storage locations are assigned consecutive addresses over the range from
00000 through FFFFF.
 Physically, memory is implemented as two independent 512Kbyte banks:
The low (even) bank and the high (odd) bank.
Hardware Organization of Memory Address Space, Data
Organization (aligned & misaligned word, double word)

 Address bits A1 through A19 select the storage location that is to be accessed. They
are applied to both banks in parallel. A0 and bank high enable () are used as bank-
select signals.
 Each of the memory banks provides half of the 8086's 16-bit data bus.
• The lower bank transfers bytes of data over data lines D0 through D7,
• while data transfers for a high bank use D8 through D15.

Logical memory organization Physical memory organization
1) Even-Address Byte Transfer
1- A0 is set to logic 0 to enable the low bank of memory.
2- BHE is set to logic 1 to disable the high bank.
3- DATA transferred to or from the lower bank over data bus lines D0 to D7
2)Odd-Address Byte Transfer
1- A0 is set to logic 1 to disable the high bank of memory.
2- BHE is set to logic 0 to enable the high bank.
3- DATA transferred to or from the high bank over data bus lines D8 to D15
3) Aligned Word Access
1- A0 is set to logic 0 to enable the high bank of memory.

2- BHE is set to logic 0 to enable the high bank.
3- DATA transferred over the complete data bus lines D0 to D15 in just one cycle
4) Misaligned Word Access
Two bus cycles are needed.
During the first bus cycle, the byte of the word located at address X + 1 in the high
bank is accessed over D8 through D15. Even though the data transfer uses data lines
D8 through D15, to the processor it is the low byte of the addressed data word.
In the second memory bus cycle, the even byte located at X + 2 in the low bank is
accessed over bus lines D0 through D7.
8086 PIN Configuration, Min
& Max Mode, 8288 Bus
Controller, 8284 System
Clock
The Pin Diagram of
the 8086
The address bus lines A0 through A15
and data bus lines D0 through D15 are
multiplexed.
The Minimum Mode is selected by
applying logic 1 to MN/MX input pin. It
is used for smaller simple CPU systems.
The Maximum Mode is selected by
applying logic 0 to MN/MX input pin. It
is used for larger multiple CPU systems.
The Pin Function of 8086 MP
8086 Minimum-Mode Block Diagram
8086 CPU Status Signals:

The four address lines (A16,
A17,A18,A19) are multiplexed with
status signals (S3,S4,S5,S6). These
status are output at the same time
that data are transferred.
The use of S3 and S4 Status Signals
Maximum Mode Interface Signals
In the maximum mode microprocessor produces
signals for implementing
multiprocessor/coprocessor system
environment .
Multiprocessor System
It means that more than one CPU exists in the
system and that each processor is executing
its own program.
8288 Bus Controller
Bus controller is used to help in
sending control signals over the
shared bus in minimum mode
especially the WR, M/IO, DT/R,
DEN ALE and INTA signals
8086 Maximum-Mode Block Diagram

8284 SYSTEM CLOCK
• To synchronize the internal and external operations of the CPU a clock (CLK) input
signal is used.
• The CLK can be generated by the 8284 clock generator IC.
• The 8086 is manufactured in three speeds: 5 MHz, 8 MHz and 10 MHz
Addressing mode, Machine
langage Coding.
Addressing mode, Machine langage Coding.
Addressing Modes: Are various ways used by the CPU to access operands in the main
memory.
The 8086 provides 7 different addressing modes.
1- Immediate Addressing Mode. In this mode, the operand is a constant data.
Note: When the instruction is assembled, the operand comes immediately after the code.
Ex: MOV CX, 4929 H
ADD AX, 2387 H
MOV AL, FF H
Note: Immediate addressing mode can be used to load data into registers except the
segment registers and flag register.
2- Register Addressing Mode. In this mode, the operand to be accessed resides in an
internal register.
Example: MOV AX, BX
This means copy the 16-bit contents of register BX (which is the source operand), to
register AX (which is the destination operand).
Ex: MOV BX, DX
MOV ES, AX
ADD AL, BH
Note: It should be noted that the source and destination registers must match in size. i.e.
MOV CL, AX , will give an error.
3- Direct Addressing Mode.
In this mode the instruction opcode is followed by an effective address (EA) instead of
data,.
so that the (EA) is used directly as the offset to calculate the physical address (PA).
Effective Address is the distance in bytes from the beginning of the segment to the
operands location
Ex: MOV CX, [1234 H]

Note: (The default segment register is DS).
Addressing Modes
4- Register Indirect Addressing Mode.

In this mode the effective address (EA) resides in either a base register (BX) or index
registers (SI, or DI).
Ex: MOV AX, [SI]

This means move the contents of the memory location that is offset is loaded in register SI
into AX.
8086 μp Memory Addressing
5- Based Relative Addressing Mode.
In this mode, the effective address (EA) of the operand is obtained by adding a direct or
indirect displacement to the content of either (BX) or (BP).
Ex: MOV [BX]+1234 H, AL

Note: The default segment register is (DS), except if (BP) is used instead of (BX), then the
segment register will be (SS).
6- Indexed Relative Addressing Mode.
In this mode, the effective address (EA) of the operand is obtained by adding a direct or
indirect displacement to the content of either (SI) or (DI).
Note: The value of displacement is used as a pointer to the starting point of an array of
data in memory and the content of specified registers as an index that selects the specific
elements in the array that is to be accessed.
Ex: MOV AL, [SI] + 1234 H

7- Based Indexed Relative Addressing Mode
Combining the based and the indexed addressing modes results in a new, more powerful
mode known as “based indexed addressing mode”.
Note: This mode can be used to access complex data structure such as 2- dimension array.
Ex: MOV AH, [BX][SI]+1234 H

8086 instructions set part 1
Data Transfer Instructions
1- MOV instruction
It can transfer a byte or word between
a) two registers
b) between register and memory.
c) It can also copy an immediate value into a register or memory.
Notes:
We can’t use this instruction to copy the contents of one segment register to another segment register
directly.
• We can’t use the code segment register CS as the destination with this instruction.
Examples:
1) What is the effect of executing this instruction MOV CX, [20H] if you know
that DS=1A00H.
Solution: Executing this instruction results in:
Physical Address = Segment Value * 10 + Offset PA=DS*10+ Offset
PA = 1A00H * 10 +20H=1A020H
CL will be loaded with the contents held at the memory address: 1A020H
(DS:20)→ (1A00:20)→(CL)
Physical Address of Next location= 1A000H+20H+1H=1A021H
CH will be loaded with the contents held at the memory address: 1A021H
{(DS:20)+1H}→ (1A00:21) →(CH)
2) Write assembly instruction program to transfer the data loaded on the
address (1A020H) to the address (1A010H), DS=1A00H.
Solution:
Physical Address = Segment Value * 10 + Offset
Physical Address=DS*10+ Offset
Offset1 = Physical Address1 – (DS*10) = 1A020H – 1A000H = 20H
Offset2 = Physical Address2 – (DS*10) = 1A010H – 1A000H = 10H
MOV AX, [20H]
MOV [10H], AX
3) Initiate or load the data 2000H into DS and ES registers.
Solution:
MOV AX, 2000H
MOV DS, AX
MOV ES, AX
2- XCHG Instruction
This instruction used to exchange the contents of the source and destination
operands (Byte or word).
You can exchange between two registers (except segment registers) or a register
and a memory location.
Example: If BX=11AAH, DS=1200H, CS=1100H, IP=0101H, [13234H]=FFH,
[13235H]=00H. what is the result of executing this instruction:
XCHG [1234H], BX
Solution:
Executing this instruction will perform the operation:
[DS:1234H] ←→ (BX)
PA=12000H+1234H=13234
After executing this instruction the contents of BX, (13234H), (13235H) will be:
BX=00FFH
[13234H]=AAH
[13235 ]=11 .
3- LEA, LDS, LES instructions:
Example: If DI=1000H, BX=20H, what is the result of executing the following
instruction:
LEA SI, [DI+BX+5H]
Solution:
when executing this instruction, it loads SI register with an offset address value.
The value of this offset is represented by the EA:
Effective Address = DI + BX + 5H
EA=1000H+20H+5H=1025H
The value of SI =1025H
Example: If IP=0100H, CS=1100H, DS=1200H, [200H]=20H, [201H]=00H,
[202H]=00H, [203H]=13H.
What is the result of executing the following instruction: LDS SI, [200H]
Solution:
SI and DS registers are loaded from the word location in memory where offset
address is 200H.
Physical Address = Segment value * 10 + Offset
PA =DS*10 + Offset
PA = 1200H *10 +200H=12200H
So PA 12200H contains 20H , 12201H contains 00H , 12202H contains 00H , 12203H
contains 13H
The content of (SI) will be = 0020H
The content of (DS) will be =1300H
Arithmetic Instructions:
1. Addition instructions:
2. Subtraction instruction:
Example 1: Assume that the content of BX, CX registers are 1234 H and 0123 H
respectively and carry flag is “0”. What is the result of executing this instruction:
SUB BX, CX and what is the value of CF
Solution:
the operation of this instruction will be as:
(BX) – (CX) → (BX)
Barrow → CF
So we get, BX=1234 H – 0123 H = 1111 H
And CF will remain “0” because there is no borrow.
8086 instructions set Part 2
3. Multiplication instruction
Example: Assume that the content of AL and CL are (-1H) and (-2H)
respectively. what result is produced in AX by executing the following
instructions:
1) MUL CL
2) IMUL CL
Solution:
1) The first instruction used 2’s complement
(AL) = -1 = 00000001b= 01H
2’s complement = 1111 1111b = FFH
(CL) = -2 = 0000 0010b = 02H
2’s complement = 1111 1110b = FEH
Therefore (AX) = FFH × FEH = FD02H
2) The second instruction multiplies the two numbers as signed numbers

(AX) = -1H × -2H = 2H = 0002H
4. Division instructions:
5- Sign- Extension Instructions:
Two instructions are available on 8086 μp
1) Convert Byte to word (CBW): . Reproduce bit 7 of AL throughout AH
7 0 7 0
AH AL
2) Convert word to double word (CWD). Reproduce bit 15 of AX throughout DX
15 0 15 0
DX AX
Example: What is the result of executing the following instructions:
MOV AL, A1H
CBW
CWD
Solution: the first instruction will load A1H into AL
(AL)= (A1H)= 1010 0001B
• executing the second instruction will result
(AL)= A1H= 1010 0001B
(AH)= 1111 1111B= FFH
• executing the third instruction will result:
(DX)= 1111 1111 1111 1111B= FFFFH
(AX)=FFA1H, (DX)=FFFFH
Logic Instructions:
6- Logic Instructions:
The 8086 μp has instructions for performing the logic operations (AND, OR, XOR,
NOT).
Logic Instructions:
Logic Instructions:
Logic Instructions:
Example:Describe the result of executing the following sequence of instructions:
MOV AL, 0101 0101B
AND AL, 0001 1111B
OR AL, C0H
XOR AL, 0FH
NOT AL
Solution:
First instruction: move the immediate operand into AL: (AL)= 0101 0101B=55H
Second instruction:(AL) = (AL). 0001 1111B= 0101 0101B . 0001 1111B= 0001 0101B= 15H
Third instruction: (AL) = (AL) + C0H = 00010101B+11000000B= 11010101B=D5H
Forth instruction: (AL) = (AL) 0FH= 11010101B+00001111B= 11011010B=DAH
Fifth instruction: (AL) = () = 00100101B=25H
Logic Instructions:
Example: Write assembly program to perform:
(1) clearing the upper 12 bits of AX
(2) Setting the bit B4 of CL.
Solution:
(3) We mean to clear, change bit or bits to zero, when a bit is ANDed with logic “0”,
the result is always “0”, while if a bit is ANDed with logic “1” its value remains
unchanged. Thus:
AND AX, 000FH.
(4) If a bit is ORed with a logic “0”, its value remains unchanged. However, if it is
ORed with a logic “1”, the result will be always “1”. Thus:
OR CL, 10H.
Shift Instructions:
7- Shift Instructions:
The 8086 μp has (4) instructions that shifts the content of an 8 or 16 bit register or
memory location one or more positions to the left or right.
The four shift instructions can perform two basic types of shift operations; the
logical shift, and arithmetic shift.
Shift Instructions:
Shift Instructions: :
Shift Instructions:
Shift Instructions:
CF MSB LSB
SAL, SHL
0
MSB LSB CF
SHR 0
MSB LSB CF
SAR
Shift Instructions:
Example: Assume that AL=10110100, CF=1, here is how the four shift
instructions affect AL and CF.
• After SAL AL, 1
AL=01101000 , CF=1
• After SAR AL, 1
AL=11011010 , CF=0
• After SHL AL, 1
AL=01101000 , CF=1
• After SHR AL, 1
AL=01011010 , CF=0
Shift Instructions:
Example: Assume that AX=091AH, BX=1234H, CF=1, and CL=02H. Determine

the new content of AX, BX, and CF after the following instructions:
SHR BX, CL
SAR AX, CL
Solution: First instruction:
BX=1234H=0001 0010 0011 0100B
Since CL=02, then BX will shifts 2 bits to the right and filled the two vacated bits
with zero. So that:
BX = 0000 0100 1000 1101B
= 048DH CF = 0
Shift Instructions:
Second instruction:
AX=091AH=0000 1001 0001 1010B
Since CL=02, then AX will shifts 2 bits to the right and filled the two vacated bits
with the MSB of AX (logic 0).
So that:
AX = 0000 0010 0100 0110B
= 0246H
CF = 1
Rotate Instructions:
8- Rotate Instructions:
CF MSB LSB
ROL
MSB LSB CF
ROR
CF MSB LSB
RCL
MSB LSB CF
RCR
Example: Assume that AL=10110100, CF=1, Here is how the 4 rotate
instruction affect AL and CF.
• After ROL AL, 1
AL = 0110 1001, CF=1
• After ROR AL, 1
AL = 0101 1010, CF=0
• After RCL AL, 1
AL = 0110 1001, CF=1
• After RCR AL, 1
AL = 1101 1010, CF=0
Example: what is the result in BX & CF after execute the following
instruction:
RCR BX, CL
Assume that CL =04H, BX=1234H, and CF=0
Solution:
BX=1234H = 0001 0010 0011 0100B
Since CL =04H, then the instruction means rotate register BX four bits through CF.
BX = 1000 0001 0010 0011 = 8123H
CF=0
8086 Stack Memory,PUSH & POP Instructions.
Memory read & write bus cycles, Idle & Wait state

Stack memory
What is a stack? why is it needed?
The stack is a section of read/write memory (RAM) used by the CPU to store
information temporarily.
Why does the CPU needs this storage area?
Because the CPU has a limited number of registers.
What is the main disadvantage of the stack?
The main disadvantage of the stack is its access time.
Since the stack is in RAM, it takes much longer to access compared to the access
time of registers. (registers are inside the CPU and RAM is outside.)
Why powerful (expensive) computers do not have a stack?
Because their CPUs have large number of registers to work with.
Stack memory
How stacks are accessed
The two main registers inside the CPU to point to the stack is a section of RAM.
• The SS (stack segment) register.
• The SP (stack pointer) register.
Every register inside the CPU can be stored in the stack, and brought back into the
CPU from the stack memory, except segment registers and SP.
• Storing a CPU register in the stack is called a push.
• Loading the contents of the stack into the CPU register is called a pop.
Stack memory
pushing onto the stack
Example:
Assuming that SP = 1236H, AX = 24B6H, DI = 85C2H, and DX = 5F93H, show the
contents of the stack as each of the following instructions is executed:
PUSH AX
PUSH DI
PUSH DX
Solution:
Stack memory
Stack memory
Review Questions:
1. Which registers are used to access the stack?
2. With each PUSH instruction, the stack pointer register SP is (circle one)
incremented/decremented by 2.
3. With each POP instruction, SP is (circle one) incremented/decremented by 2.
4. List three possible logical addresses corresponding to physical address 143F0.
5. The ADD instruction can affect which bits of the flag register?
6. The carry flag will be set to 1 in an 8-bit ADD if there is a carry out from bit ___.
7. CF will be set to 1 in a 16-bit ADD if there is a carry out from bit ____.
BUS CYCLES & TIME STATES
Bus Cycle: It is A Sequence of events at which the CPU communicates with an
external device, which starts with an address being output on the system bus followed
by a read or write data transfer.
Types of bus cycles of the 8086 CPU:

1) Memory Read Bus Cycle
2) Memory Write Bus Cycle
The bus cycle of the 8086 microprocessor consists of at least four clock periods.
These four time states are called T1, T2, T3 and T4.
BUS CYCLES &TIME STATES
Memory Read cycle of the 8086 CPU
• T1 state-read cycle begins
 Address output on A0-A19
 Pulse produced at ALE--address should be latched in external circuitry on
trailing edge of ALE
 IO/set to 0 memory bus cycle
 DT/set to 0 set external data bus control circuitry for receive mode (read)
• T2 state
 Status code output on S3-S6
 AD0 through AD7 tri-stated in preparation for data bus operation
 set to 0 read cycle
 set to 0 enable external data bus control circuitry
Memory Read cycle of the 8086 CPU
• T3 state
 Data on D0-D7 read by the MPU
• T4 state-read cycle finishes
 returns to 1 inactive level
 Complete address/data bus tri-stated
 IO/returned to 1 IO bus cycle
 returned to 1inactive level
 DT/returns to 1 transmit level
Minimum Mode Read Bus Cycle
Memory write cycle of the 8086 CPU
•T1 state-write cycle begins
 Address output on A0-A19
 Pulse produced at ALE and address latched in external circuitry on trailing edge of ALE
 IO/ set to 0 memory bus cycle
 DT/ remains at 1 external data bus control circuitry for transmit mode (write)
• T2 state
 Status code output on S3-S6
 AD0 through AD7 transitioned to data bus and write data placed on bus
 set to 0 enable external data bus control circuitry
 set to 0 write cycle
Memory write cycle of the 8086 CPU

• T3 or T4 state
 Data on D0-D7 written into memory (memory decides when!)
• T4 state—write cycle finishes
 returns to 1 inactive level
 Complete address/data bus tri-stated
 IO/ returned to 1 IO bus cycle
 returned to 1 inactive level
Minimum Mode Write Bus Cycle
Minimum Mode Read Bus Cycle

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‫مادة الفصل الثاني‬

A typical Assembly language program consist of at least three segments:

Logical Address Consists of a segment value and an offset address.

The Code segment:

1.Start with CS.

2.Shift left CS.

(a)24F6:634A (c) PA= (segment value * 10 + offset) = (24F60 + 634A) = 2B2AA

Little Endian Convention:

MOV AX, 35F3H

DS:1500 = F3H DS:1501 = 35H

A single physical address can belong to many different logical addresses. E. g.

Logical address (hex) Physical address (hex)

LECTURER. RIYADH BASSIL

• while data transfers for a high bank use D8 through D15.

1- A0 is set to logic 0 to enable the high bank of memory.

8086 CPU Status Signals:

8086 Maximum-Mode Block Diagram

Ex: MOV CX, [1234 H]

4- Register Indirect Addressing Mode.

Ex: MOV AX, [SI]

Ex: MOV [BX]+1234 H, AL

Ex: MOV AL, [SI] + 1234 H

Ex: MOV AH, [BX][SI]+1234 H

2) The second instruction multiplies the two numbers as signed numbers

Example: Assume that AX=091AH, BX=1234H, CF=1, and CL=02H. Determine

LECTURER. RIYADH BASSIL

• The SS (stack segment) register.

• The SP (stack pointer) register.

• Storing a CPU register in the stack is called a push.

Types of bus cycles of the 8086 CPU:

Minimum Mode Read Bus Cycle

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