Analysis of Mixed-Signal IC

Layout

References:
1. Alan Hasting, “The Art of Analog Layout, “Prentice Hall,
ISBN 0-13-087061-6, 2001
2. Behzad Razavi, “Design of Analog CMOS Integrated Circuits,
“McDraw-Hill, ISBN-0-07-118839-8, 2001
3. Johnson Liu, “Mixed-Signal IC Layout, “Workshop on Fully
Layout Technology, Mar. 23, 2002.
4. IEEE Journals and Conferences Papers.
5. USA Patents
 Analysis of Mixed-Signal IC Layout
Contents:
Chapter
1. CMOS Processing Flow
2. Layout Design Rules
3. Analog Layout Consideration
4. Layout of MOS Transistor
5. Layout of Digital Circuits
6. Layout of Resistor
7. Layout of Capacitor
8. Layout of Inductor
9. Latch-up
10.Analog Cells/Macros Layout
11.Power Distribution and Signal-Integrity
12.Floor Planning of Mixed-Signal IC
13.Noise Sources of Mixed-Signal IC
 Chapter 1
CMOS Processing Flow
•0.25um 1P5M
• 0.8um 1P6M
• 0.13um 1P7M
• 0.09um
• Copper Interconnection
• Mixed-Signal/RF
• CMOS Processing Flow
0.25um 1P5M
0.18um 1P6M
0.13um 1P7M
 0.09um
• Manufactured on 300mm wafers
• Include high performance, low-power, mixed-
signal/RF, and embedded memory option
• Triple gate oxide option
• With 70-75% linear shrinkage
• Two-times performance improvement, compared to
TSMC’s 0.13-micron technology
• Core supply voltage : 1.0V ~ 1.2V
• I/O and analog blocks : 1.8V ~ 3.3V
• Multiple threshold voltage (Vt) option
 0.09um
• Ni-salicide for better sheet resistance (Rs) in narrow line
widths
• Nine-layer copper interconnect, with an extra
redistribution layer optional for flip-chip package
• Low-k dielectrics with k 2.9 for the lowest RC delay and
power consumption
• MiM capacitor
• High resistance resistor
• High Q inductor and varactor
• DNW (deep N-well) bipolar junction transistor
• Embedded 1TRAMTM and 6T/8T SRAM
• 6t SRAM has ultra-high-density (UHD) cell high-cell-
current (HC) cell for different application and flash
 Copper Interconnection
• The electrical resistance of copper interconnection is less
than two-thirds that of tungsten interconnection
• The series resistance of copper via runs as low 20% that
of tungsten plugs.
• Which are commonly used for power, clock routing,
bonding pads and 15% RC delay reduction at the 0.18-
micron process.
• Provide top two-layer and all-layer copper option at the
0.15-micron process.
• The lower electrical resistance leads to improved power
distribution, device performance throughout the clip.
• Improves the electro migration resistance, a major concern
in IC’s long term reliability, by as much as 50 times
• Reduce cross-talk by providing a better control over the
tight metal pitch
Mixed Signal/RF
Periodic Table
Semiconductor
Simplified Two-Dimensional Silicon
Crystal Structure
Thermal Generation in Intrinsic Silicon
Selected Properties of Group-IV
Elements
Crystal Structure of Phosphorus-Doped
Silicon
Crystal Structure of Boron-Doped Silicon
Extrinsic Semiconductor Terminology
Diffusion and Drift
 PN Junction
Ohmic
contact
 PN Junction
Carrier Population in silicon
• before the junction is assembled.
• After the junction is assembled.
PN Junction
Forward biased PN Junction
Diode conduction characteristics
NPN and PNP transistor
Current flow in an NPN transistor
CMOS PROCESSING
Silicon wafer
Czchralski method- single-crystal method
• starts with a seed of single crystal silicon, and the pull rate and speed of
rotation determine the diameter of the crystal rod or ingot.
• heavily doped silicon is added to the melt before the single-crystal ingot is
pulled
• the ingot is cut into wafers using a large diamonds saw
• p- is doped around NA 2x10¯²¹ donor/m³, resistivity 10-20Ω ٠ cm.
(100) and (111) silicon wafers
Diamond Lattice Unit Cell
Identification of (100) and (111) planes
Epitaxial
The surface of wafer might be doped more heavily, and a
single crystal epitaxial layer of the opposite type might be grown
over its surface.

Photolithography

Selected portion of silicon wafer cab masked out so that some type
of processing step can be applied to the remaining areas.

- Grow a thin oxide( SiO2 ) to protect the surface

 Photomask exposure Using an Aligner

UV source

Lens
Photomask

Lens
Sensitized
wafer

Photoresist
• negative photoresist, exposed photoresist remains after the masking
• positive photoresist, exposed photoresist is dissolved by organic solvents,
the photoresist still remains where the mask was opaque.
• By using both positive and negative photoresist, a single mask can
sometimes be used for two steps.
 Diffusion

Forming an n well by diffusing phosphorus from a gas into the

silicon, through the opening in the SiO2
• Dopant is Phosphorus for n-well, Arsenic takes much longer time to
diffuse.
• 900-1100°C, high temperature causes dopant to diffuse vertically
and laterally. Dopant concentration is the greatest at surface.
• Boron for p-well.
 Ion Implementation

• Allows more independent control over concentration and the thickness of doped
region
• Ion beams are focused and accelerated at 10 keV and 1MeV.
• Lattice damage due to nuclear collision result in displacement of sbstrate atoms
• Narrow profile result in heavy concentration (Arsenic with 100keV, 0.06 um ±
0.02 um.)
• Greater control over doping level.
• Much smaller side wall diffusion, allows device to be more closely spaced,
minimized overlap between gate source and gate-drain regions.
 Annealing

Dopant profiles after ion implementation both before and after annealing
• 1000°C fir 15-30 minutes, then cooled down.
• broaden concentration profile, make profile more uniform.
• Solve the above mentioned problems in ion implementation.
 Field-implementation

• Chemical Vapor Deposition

• E.g. Si3N4 deposited during a gas-phase reaction at about 800°C.

The cross Section when field-implants are being formed.

• Filled Implant where field-oxide grown.

• Guarantee silicon under field-oxide will never invert when the
conductor over the field-oxide has large voltage.
• Leakage between junction of separate transistors in the substrate
region is intended to unconnected.
 Growing Field-Oxide: thermal oxide
Wet process: water vapor diffuses into silicon
Si+2H2O SiO2+2H2
Dry process: oxygen introduced over wafer, slightly
higher temperature than wet process
Si+O2SiO2

The cross section after the field-oxide has been grown

Grow 0.1um of Oxide on (100) Silicon
Ambient 800°C 900°C 1000°C 1100°C 1200°C

Dry O 2 30hr 6hr 1.7hr 40min 15min

Wet O 2 1.7hr 20min 6min    

Step in Oxide Grown and Removal
Effects of Patterned Oxidation on Wafer Topology

• SiO2 takes up approximately 2.2 times the volume of

the original silicon, causes SiO2 to extend approximately
45 percent into, and 55 percent above surface.
• Wet process is faster because H2O diffuses faster in
silicon than O2 does.
•Dry process result in denser, higher-quality SiO2 that is
less porous.
Local Oxidation of Silicon (LOCOS)
Process
 Kooi Effect
a) Kooi effect cause by nitride that grows under the
bird’s beak.
b) Preventing formation of gate oxide during
subsequent oxidation.
 Wet Etching and Dry Etching
a) Isotropic wet etching
b) Anisotropic dry etching
Reactive Ion Etching Apparatus
Gate-Oxide and threshold-Voltage Adjust

Cross section after the thin gate-oxide

growth and threshold-adjust implant.
 Polysilicon Gate Formation

Cross section after depositing and patterning the polysilicon gate.

• Chemical deposition of polysilicon with silane (SiH4) gas.
• 650°C, noncrystaline or armophous. (1000-1250 °C on silicon to
create single-crystal silicon)
• Ion implemented with Arsenic to increase it’s conductivity (10-30Ω/[])
Silicidation
 Implanting Junction

Cross section after ion-implanting the p+ junctions.

Formation of Diffused PN- Junction Diodes
 Cross section after ion-implanting n+ junctions

• Boron implementation to form p+region. self-aligned to poly edge, resulting in

very little overlap.
• p+ also for substrate Vss contact to prevent latch-up
• Arsenic implemented to from n+ region.
• N+ also for n-well VDD contact to prevent latch-up.
• After all junction have been implanted, the complete wafer is covered in CVD
SiO2. 500°C, 0.025-0.5 um.
• Next step, open contact hole.
Effects of Dopant-Enhanced Oxidation

Doping Profile of a Planar Diffusion

Self-Aligned Source and Drain Region
Formation of an N-Buried Layer (NBL)
 Depositing and Patterning Metal
• Aluminum (AI) for interconnection
• Evaporation techniques in a vacuum, the heat for
evaporation is produced by electron-beam in a sputtering
system.
• Low-temperature annealing (550°C), give better bonds
between metal and silicon.
Formation of First-Level Metal
Step Coverage of Evaporated Aluminum
Cross Section of Double-Metal Single-Poly
 Overglass Deposition
Final Passivation CVD SiO2 is deposited, often
an additional Si3N4 is deposited for better
impervious to moisture.

Final cross section of an example CMOS microcircuit.

Cross-section
Step1 : N-Well (NW)

Cross-section
Step2: Thin Oxide (OD)

Cross-section
Step3: Poly (PO)

Cross-section
Step4: P+S/D implant (PP)

Cross-section
Step5: N+S/D implant (NP)

Cross-section
Step6: Contact (CO)

Cross-section
Step7: Metal-1 (M1)
Step8: Via1 Hole
Step9: Metal-2 (M2)
LDD allow very small transistor without suffering from “hot electron”
The surface has to be planarized before deposition of another layer
Etched with a solution that has the same etching rate for photoresist & oxide
• two layer method, high quality due to planarization step
• LDD: NMOS preventing hot-electron phenomena
• optimal threshold voltage both PMOS & NMOS through twin-well
• good latch-up protection by minimizing, the lateral voltage drop inside the
wells