EN5500 – Computer Systems

Processor Design -
Micro-Programmed Controlled

Ajith Pasqual
pasqual@uom.lk

M.Sc. In Electronics and Automation

Reference: Structured Computer Organization - Tannebaum

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 Factors to consider ..
• ISA – Most important stage in processor
design
– Need to finalize exactly what this processor is
supposed to do
– What type of data would be processed?
• Integer/floating point/char/strings …
– What type of instructions would be required to
achieve the above
• Integer/floating point instructions
– Within a set of constraints (E.g. amount of
memory)

End of this process gives the Instruction Set of the

Processor
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Data Path consists of ALU,
its inputs and its outputs.

- Contains number of 32 bit

registers (E.g. PC, SP, MDR)
- The registers are accessible
only at the micro-
architecture level by the
micro-program.
ALU & Shifter Control Signals
F0 & F1 – ALU operation
ENA & ENB – individually enable
inputs
INVA – Inverting the left i/p
INC – Force a carry into lower bit
SLL8 – Logical Shift Left (8bit)
SRA1 – Shift Right – 1 bit MSB
unchanged.
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-A means 2’s
complement of A

Note the limitations

of the instructions:
E.g. A-B is not
possible.
Subtrahend must
always be A (i.e. the
value in H Register)
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 Timing Waveforms
• The CPU must provide the memory control
signals in such a way as to synchronize its
own internal clocked operations with the read
and write operations of memory.
• This means that the access time and the write
cycle time of the memory must be related
within the CPU to a period equal to a fixed
number of CPU clock pulse periods.
• Consider an example:
– CPU Speed : 50MHz
– Access time : 65ns
– Write cycle time : 75ns.

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 Instruction Fetch Unit (IFU)

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 IFU Logic (FSM)

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