+ Module 1

Introduction
Computer Architecture
Computer Organization
• Attributes of a system visible to the • Instruction set, number of
programmer bits used to represent
• Have a direct impact on the logical various data types, I/O
execution of a program mechanisms, techniques for
addressing memory

Architectural
Computer
attributes
Architecture
include:

Organizational
Computer
attributes
Organization
include:

• Hardware details transparent to the • The operational units and

programmer, control signals, interfaces their interconnections that
between the computer and peripherals, realize the architectural
memory technology used specifications
+
IBM System
370 Architecture
 IBM System/370 architecture
 Was introduced in 1970
 Included a number of models
 Could upgrade to a more expensive, faster model without having to abandon
original software
 New models are introduced with improved technology, but retain the same
architecture so that the customer’s software investment is protected
 Architecture has survived to this day as the architecture of IBM’s mainframe
product line
+
Structure and Function

 Hierarchical system
 Structure
 Set of interrelated subsystems
 The way in which components
 Hierarchical nature of complex relate to each other
systems is essential to both their
 Function
design and their description
 The operation of individual
 Designer need only deal with a components as part of the
particular level of the system at a structure
time
 Concerned with structure and
function at each level
+
Function

 A computer can perform four

basic functions:

● Data processing
● Data storage
● Data movement
● Control
+
Operations

(a)
Data movement
+
Operations

(b)
Data storage
+

Operations

(c)
Data processing
+

Operations

(d)
Control
 The
Computer
Structure
+
 CPU – controls the operation of
the computer and performs its data
There are four processing functions
main structural
components  Main Memory – stores data
of the computer:  I/O – moves data between the
computer and its external
environment

 System Interconnection – some

mechanism that provides for
communication among CPU, main
memory, and I/O
+  Control Unit
CPU  Controls the operation of the CPU and
hence the computer
Major structural
 Arithmetic and Logic Unit (ALU)
components:  Performs the computer’s data processing
function

 Registers
 Provide storage internal to the CPU

 CPU Interconnection
 Some mechanism that provides for
communication among the control unit,
ALU, and registers
 Computer Evolution
+
and Performance
+
History of Computers
First Generation: Vacuum Tubes
 ENIAC
 Electronic Numerical Integrator And Computer
 Designed and constructed at the University of Pennsylvania
 Started in 1943 – completed in 1946
 By John Mauchly and John Eckert

 World’s first general purpose electronic digital computer

 Army’s Ballistics Research Laboratory (BRL) needed a way to supply trajectory tables for new
weapons accurately and within a reasonable time frame
 Was not finished in time to be used in the war effort

 Its first task was to perform a series of calculations that were used to help determine the
feasibility of the hydrogen bomb

 Continued to operate under BRL management until 1955 when it was disassembled
 ENIAC

Major
Memory drawback
drawback
consisted was
Occupied was the
the need
need
Contained Capable of 20 accumulators,
1500 Decimal
more
more of
of each
each for manual
Weighed square 140 kW rather
than 5000 capable programming
30 feet Power than
18,000 additions of
tons of consumption binary by setting
vacuum
vacuum per
per holding
holding switches
floor machine
tubes second a and
space
10 digit plugging/
number
number unplugging
cables
+
John von Neumann
EDVAC (Electronic Discrete Variable Computer)
 First publication of the idea was in 1945

 Stored program concept

 Attributed to ENIAC designers, most notably the mathematician John von
Neumann
 Program represented in a form suitable for storing in memory alongside
the data

 IAS computer
 Princeton Institute for Advanced Studies
 Prototype of all subsequent general-purpose computers
 Completed in 1952
Structure of von Neumann Machine
+
IAS Memory Formats
 The memory of the IAS consists
of 1000 storage locations (called
words) of 40 bits each
 Both data and instructions are stored
there
 Numbers are represented in binary
form and each instruction is a binary
code
+
Structure
of
IAS
Computer
+ Registers
Memory buffer register • Contains a word to be stored in memory or sent to the I/O unit
(MBR) • Or is used to receive a word from memory or from the I/O unit

Memory address register • Specifies the address in memory of the word to be written from or read
(MAR) into the MBR

Instruction register (IR) • Contains the 8-bit opcode instruction being executed

Instruction buffer register • Employed to temporarily hold the right-hand instruction from a word in
(IBR) memory

• Contains the address of the next instruction pair to be fetched from

Program counter (PC) memory

Accumulator (AC) and • Employed to temporarily hold operands and results of ALU operations
multiplier quotient (MQ)
+

IAS
Operations
+

Table 2.1

The IAS
Instruction
Set

Table 2.1 The IAS Instruction Set

+
Commercial Computers
UNIVAC
 1947 – Eckert and Mauchly formed the Eckert-Mauchly Computer Corporation
to manufacture computers commercially

 UNIVAC I (Universal Automatic Computer)

 First successful commercial computer
 Was intended for both scientific and commercial applications
 Commissioned by the US Bureau of Census for 1950 calculations

 The Eckert-Mauchly Computer Corporation became part of the UNIVAC

division of the Sperry-Rand Corporation

 UNIVAC II – delivered in the late 1950’s

 Had greater memory capacity and higher performance

 Backward compatible
+
 Was the major manufacturer of
punched-card processing equipment

 Delivered its first electronic stored-

program computer (701) in 1953
 Intended primarily for scientific
applications

 Introduced 702 product in 1955

 Hardware features made it suitable
IBM
to business applications

 Series of 700/7000 computers

established IBM as the
overwhelmingly dominant
computer manufacturer
+
History of Computers
Second Generation: Transistors
 Smaller

 Cheaper

 Dissipates less heat than a vacuum tube

 Is a solid state device made from silicon

 Was invented at Bell Labs in 1947

 It was not until the late 1950’s that fully transistorized computers
were commercially available
 Table 2.2  
Computer Generations

+
Computer Generations
+
Second Generation Computers

 Introduced:  Appearance of the Digital

 More complex arithmetic and Equipment Corporation (DEC) in
logic units and control units 1957
 The use of high-level
programming languages  PDP-1 was DEC’s first computer
 Provision of system software
 This began the mini-computer
which provided the ability to:
phenomenon that would become
 load programs so prominent in the third
 move data to peripherals and generation
libraries
 perform common
computations
 Table 2.3  
Example
Members of the
IBM 700/7000 Series
 

Table 2.3 Example Members of the IBM 700/7000 Series

 IBM
7094
Configuration
History of Computers
Third Generation: Integrated Circuits

 1958 – the invention of the integrated circuit

 Discrete component
 Single, self-contained transistor
 Manufactured separately, packaged in their own containers, and soldered
or wired together onto masonite-like circuit boards
 Manufacturing process was expensive and cumbersome

 The two most important members of the third generation were the
IBM System/360 and the DEC PDP-8
+
Microelectronics
+ 
Integrated
Circuits
 Data storage – provided by
memory cells
 Data processing – provided by
gates
 Data movement – the paths among
components are used to move data
from memory to memory and from
memory through gates to memory
 Control – the paths among
components can carry control
signals
A computer consists of gates,
memory cells, and
interconnections among these
elements
 The gates and memory cells are
constructed of simple digital
electronic components
 Exploits the fact that such
components as transistors, resistors,
and conductors can be fabricated
from a semiconductor such as silicon
 Many transistors can be produced at
the same time on a single wafer of
silicon
 Transistors can be connected with a
processor metallization to form
circuits
+
Wafer,
Chip,
and
Gate
Relationship
+
Chip Growth
Moore’s Law

1965; Gordon Moore – co-founder of Intel

Observed number of transistors that could be put

on a single chip was doubling every year

Consequences of Moore’s law:

The pace slowed to a
doubling every 18
months in the 1970’s
The cost of Computer
but has sustained computer logic
The electrical
Reduction in
path length is becomes smaller
that rate ever since and memory and is more power and Fewer interchip
shortened, convenient to use
circuitry has cooling connections
increasing in a variety of
fallen at a requirements
operating speed environments
dramatic rate
+ LSI
Large
Scale
Later Integration

Generations
VLSI
Very Large
Scale
Integration

ULSI
Semiconductor Memory Ultra Large
Microprocessors Scale
Integration
+ Semiconductor Memory

In 1970 Fairchild produced the first relatively capacious semiconductor memory

Chip was about the size of Could hold 256 bits of
Non-destructive Much faster than core
a single core memory

In 1974 the price per bit of semiconductor memory dropped below the price per bit of core
There has been a continuing and rapid decline in memory
Developments in memory and processor technologies
memory cost accompanied by a corresponding increase
changed the nature of computers in less than a decade
in physical memory density

Since 1970 semiconductor memory has been through 13 generations

Each generation has provided four times the storage density of the previous generation, accompanied by declining
cost per bit and declining access time
+
Microprocessors
 The density of elements on processor chips continued to rise
 More and more elements were placed on each chip so that fewer and fewer
chips were needed to construct a single computer processor

 1971 Intel developed 4004

 First chip to contain all of the components of a CPU on a single chip
 Birth of microprocessor

 1972 Intel developed 8008

 First 8-bit microprocessor

 1974 Intel developed 8080

 First general purpose microprocessor
 Faster, has a richer instruction set, has a large addressing capability
Evolution of Intel Microprocessors

a. 1970s Processors

b. 1980s
Evolution of Intel Microprocessors

c. 1990s Processors

d. Recent Processors
+
System Clock
+ Table
Performance Factors 2.9
and
System Attributes
Benchmarks
For example, consider this high-level language statement:

A = B + C /* assume all quantities in main memory */

With a traditional instruction set architecture, referred to as a complex instruction

set computer (CISC), this instruction can be compiled into one processor
instruction:

add mem(B), mem(C), mem (A)

On a typical RISC machine, the compilation would look something like

this:
load mem(B), reg(1);
load mem(C), reg(2);
add reg(1), reg(2), reg(3);
store reg(3), mem (A)
+ Desirable Benchmark Characteristics

Written in a high-level language, making it portable across different

machines

Representative of a particular kind of programming style, such as system

programming, numerical programming, or commercial programming

Can be measured easily

Has wide distribution

+
System Performance Evaluation
Corporation (SPEC)
 Benchmark suite
 A collection of programs, defined in a high-level language
 Attempts to provide a representative test of a computer in a particular
application or system programming area

 SPEC
 An industry consortium
 Defines and maintains the best known collection of benchmark suites
 Performance measurements are widely used for comparison and research
purposes
+  Best known SPEC benchmark suite

 Industry standard suite for processor

intensive applications
SPEC  Appropriate for measuring performance for
applications that spend most of their time
doing computation rather than I/O

CPU2006  Consists of 17 floating point programs

written in C, C++, and Fortran and 12 integer
programs written in C and C++

 Suite contains over 3 million lines of code

 Fifth generation of processor intensive suites

from SPEC
+  Gene Amdahl [AMDA67]

 Deals with the potential speedup of a

program using multiple processors compared
to a single processor
Amdahl’s  Illustrates the problems facing industry in the
development of multi-core machines
Law  Software must be adapted to a highly
parallel execution environment to exploit
the power of parallel processing

 Can be generalized to evaluate and design

technical improvement in a computer system
+
Amdahl’s Law
+
Little’s Law
 Fundamental and simple relation with broad applications

 Can be applied to almost any system that is statistically in steady

state, and in which there is no leakage

 Queuing system
 If server is idle an item is served immediately, otherwise an arriving item
joins a queue
 There can be a single queue for a single server or for multiple servers, or
multiples queues with one being for each of multiple servers

 Average number of items in a queuing system equals the average

rate at which items arrive multiplied by the time that an item
spends in the system
 Relationship requires very few assumptions
 Because of its simplicity and generality it is extremely useful
+ Summary
Chapter 2
 First generation computers
 Vacuum tubes
 Second generation computers
 Transistors
 Third generation computers
 Integrated circuits
 Performance designs
 Microprocessor speed
 Performance balance
 Chip organization and
architecture
Computer Evolution
and Performance
 Multi-core
 MICs
 GPGPUs
 Evolution of the Intel x86
 Embedded systems
 ARM evolution
 Performance assessment
 Clock speed and instructions per
second
 Benchmarks
 Amdahl’s Law
 Little’s Law
 A Top-Level
View of Computer
Function and
+
Interconnection
+
Computer Components
 Contemporary computer designs are based on concepts developed by
John von Neumann at the Institute for Advanced Studies, Princeton

 Referred to as the von Neumann architecture and is based on three

key concepts:
 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location, without regard to
the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly modified) from
one instruction to the next

 Hardwired program
 The result of the process of connecting the various components in the
desired configuration as form of programming. The resulting “program” is
in the form of hardware and is termed a hardwired program.
+
Hardware
and Software
Approaches
 Software Software

●
A sequence of codes or instructions
●
Part of the hardware interprets each instruction and generates control signals
Provide a new sequence of codes for each new program instead of rewiring
I/O
●

the hardware
Components

Major components:
+

●
CPU
●
Instruction interpreter
●
Module of general-purpose arithmetic and logic functions
●
I/O Components
●
Input module
●
Contains basic components for accepting data and instructions and converting them into an internal form of signals usable by the system
●
Output module
●
Means of reporting results
 Memory address Memory buffer MEMORY
register (MAR) register (MBR)
Specifies the Contains the data
address in to be written into
memory or
memory for the
receives the data
next read or
read from
write memory
MAR

I/O buffer register

I/O address (I/OBR)
+ register (I/OAR) Used for the
Specifies a exchange of
particular data between
an I/O module MBR
I/O device and the CPU
 Computer
Components:
Top Level
View
+
Basic Instruction Cycle
+
Fetch Cycle
 At the beginning of each instruction cycle the processor fetches an
instruction from memory

 The program counter (PC) holds the address of the instruction to be

fetched next

 The processor increments the PC after each instruction fetch so that

it will fetch the next instruction in sequence

 The fetched instruction is loaded into the instruction register (IR)

 The instruction contains bits that specify the action the processor is
to take. The processor interprets the instruction and performs the
required action
Action Categories
●
Data transferred to or
●
Data transferred
from a peripheral
from processor to
device by transferring
memory or from between the processor
memory to processor and an I/O module

Processor- Processor-
memory I/O

Data
Control
processing
●
An instruction may ●
The processor
specify that the may perform some
sequence of arithmetic or logic
execution be altered operation on data
+
+
Example
of
Program
Execution
+
Instruction Cycle State Diagram
+
Classes of Interrupts
Program Flow Control
+
Transfer of Control via Interrupts
+
Instruction Cycle With Interrupts
+

Program
Timing:
Short I/O
Wait
+

Program
Timing:
Long I/O
Wait
Instruction Cycle State Diagram
With Interrupts
 Transfer of
Control

Multiple
Interrupts

+
+ Time Sequence of Ex
Multiple Interrupts am
ple
+
I/O Function
 I/O module can exchange data directly with the processor

 Processor can read data from or write data to an I/O module

 Processor identifies a specific device that is controlled by a particular I/O
module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to occur directly

with memory
 The processor grants to an I/O module the authority to read from or write
to memory so that the I/O memory transfer can occur without tying up the
processor
 The I/O module issues read or write commands to memory relieving the
processor of responsibility for the exchange
 This operation is known as direct memory access (DMA)
+ Computer
Modules
The interconnection structure must support the following
types of transfers:

I/O to or
Memory to Processor to I/O to Processor to
from
processor memory processor I/O
memory
An I/O
Process Process module is
or reads Process or reads allowed to
Process
an or data exchange
or data directly
instructi writes a from an with
sends memory
on or a unit of I/O without
data to
unit of data to device going

data via an the I/O through the

memor processor
from I/O device using direct
y memory
memory module access
 Signals
Signals transmitted
transmitted by by any
any one
one device
device
munication
munication pathway
pathway are
are available
available for
for reception
reception byby all
all
cting
cting two
two or
or more
more devices
devices other
other devices
devices attached
attached toto the
the bus
bus

Bus
characteristic
characteristic is
is that
that it
it is
is aa If
If two
two devices
devices transmit
transmit during
during the
the
dd transmission same
same time period their signals will
time period their signals
transmission medium
medium will
overlap and become garbled
overlap and become garbled

lly
lly consists

line
consists of
unication
unication lines
line is
of multiple
lines
is capable
multiple

capable of
of
Computer
Computer systems
number of
number
systems contain
of different
provide
contain aa
different buses
buses that
that
Inter
provide pathways
pathways between

conn
mitting between
mitting signals
signals components
senting components at
at various
various levels
levels of
of
senting binary
binary 11 and
and the
yy 00 the computer
computer system
system hierarchy
hierarchy

System
System bus
A
A bus
bus
bus that
that connects
connects major
major
The
The most
computer
most common
common
computer interconnection
interconnection
ectio
structures
structures are
are based
based on
on the

n
computer the
computer components
components use of one or more system
(processor, use of one or more system
(processor, memory,
memory, I/O)
I/O) buses
buses
Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be transferred at a

time

 The width of the data bus

is a key factor in
determining overall
system performance
+ Address Bus
 Used to designate the source or
destination of the data on the data bus
 If the processor wishes to read a
word of data from memory it puts
the address of the desired word on
the address lines
 Width determines the maximum
possible memory capacity of the
system
 Also used to address I/O ports
 The higher order bits are used to
select a particular module on the
bus and the lower order bits select
a memory location or I/O port
within the module
Control Bus
 Used to control the access and the
use of the data and address lines
 Because the data and address lines
are shared by all components there
must be a means of controlling their
use
 Control signals transmit both
command and timing information
among system modules
 Timing signals indicate the validity
of data and address information
 Command signals specify operations
to be performed
Bus Interconnection Scheme
Bus
Conf
igura
tions
+
Elements of Bus Design
 Timing of
Synchronous
Bus Operations
 Timing of
Asynchronous
Bus
Operations
+
Point-to-Point Interconnect

Principal reason for change At higher and higher data rates

was the electrical constraints it becomes increasingly difficult
encountered with increasing to perform the synchronization
the frequency of wide and arbitration functions in a
synchronous buses timely fashion

A conventional shared bus on the

same chip magnified the
difficulties of increasing bus data
rate and reducing bus latency to
keep up with the processors

Has lower latency,

higher data rate, and
better scalability