Input-Output Organization

1
 Overview
• Peripheral Devices
• Input-Output Interface
• Asynchronous Data Transfer
• Modes of Transfer
• Priority Interrupts
• Direct Memory Access
• Input-Output Processor
• Serial Communication
2
Peripheral Devices

3
 Peripheral Devices
• Efficient communication between CPU & outside
• Gets inputs external sources
– Keyboard, mouse, touch screen, barcode reader,
modem, NIC, Mic, disk, tape
• Send outputs
– Monitor, NIC, Printer, Modem, Speaker, disk, tape
• Peripheral devices extremely slow to CPU
– Large amount of data prepares in advance to transfer
to CPU
– The result of programs transfer to high-speed disk
and then to the peripheral like printers
4
 Peripheral
• On-line devices
– Devices under direct computer control
– Read/write information to memory on CPU command
• Peripheral
– Devices attached to the computer
– Electromechanical/electromagnetic
– Monitor/Keyboard
– Printer
– Magnetic tape
– Magnetic disk

5
ASCII Alphanumeric Characters
• American Standard Code for Information
Interchange
• 128 characters
– 94 printable
• 26 Uppercase, 26 Lowercase, 10 numeric, 32 special (%, *)
– 34 non-printable (control)
• Abbreviated names
– Format characters (BS - backspace, CR - carriage return)
– Information separators (RS - record separators, FS - file
separators)
– Communication controls (STX - start of text, ETX - end of text)

6
ASCII Alphanumeric Characters
• Computer uses 8 bits for a character
• Additional bit?
– As the parity for character
– For other special characters (Italic, Greek)

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 Input-Output Interface
• Transfer information between internal storage
and external peripherals
• Resolves the difference between CPU and
peripherals
– Signal value changes
– Transfer rate mapping
– Data code format mapping
– Control operating modes (not to disturb each other)
• Interfaces supervise and synchronize transfers
• Lies between processor bus and peripheral
device (or its controller)

8
 O/I Bus and Interface Modules
• I/O bus consists of
– Data lines
– Control lines
– Address lines
• Each peripheral is associated with its interface
unit
– Decode address and control received
– Interrupts for the device
– Provide signals for device
– Synchronize and supervise data flow
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 O/I Bus and Interface Modules
CPU Memory
Independent I/O Bus memory
bus

Interface Interface Separate I/O instructions (in,out)

Peripheral Peripheral

CPU Lines distinguish between

common memory I/O and memory transfers
& I/O bus
40 Mbytes/sec
VME bus optimistically
Multibus-II
Memory Interface Interface Nubus 10 MIP processor
completely
saturates the bus!
Peripheral Peripheral 10
Input-Output Interface

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 I/O Bus and Interface Modules
• Each interface has own address
• Processor places address on address lines
• Corresponding peripheral responds while others
are deactivated
• Same time processor provides function code on
control lines
• Interface executes function on peripheral
• 4 main command types
– Control commands, status, output data, input data

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 I/O vs. Memory Bus
3 ways to communicate with I/O and
memory
– Use two separate buses
• Uses separate I/O processor
• Memory communicate with both IOP and CPU via
memory bus
• IOP has separate set of data, address and control
lines with peripheral interfaces
– Use common bus but separate control lines
– Common bus and control lines

13
 Isolated vs. Memory-Mapped I/O
• Uses common bus for data transfer
• Isolated I/O
– Uses separate Memory or I/O R/W lines
– Separate I/O instruction set
– Own address spaces for memory and I/O
– Complex but high flexible
• Memory mapped I/O
– Uses same address space with memory
– Only one set of R/W signals
– Interface registers considered as a part of memory system
– Reduces memory address space available
– Same instruction set

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 I/O mapped I/O (Isolated I/O)
• Common bus(data and address) for I/O and memory but separate read and write
control lines for I/O.
• when CPU decode instruction then if data is for I/O then it places the address on the
address line and set I/O read or write control line (I/O)/M’=1) on due to which data
transfer occurs between CPU and I/O.
• the address space of memory and I/O is isolated/separted
• The address for I/O here is called ports. Here we have different read-write instruction
for both I/O and memory.
• In 8085, I/O mapped I/O uses 8 bit address. It is copied(duplicate) both lower and
higher address bus.

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 Memory Mapped I/O
• In this case every bus in common due to which the same set of
instructions work for memory and I/O.
• Hence we manipulate I/O same as memory and both have same
address space, due to which addressing capability of memory
become less because some part is occupied by the I/O.
• LDA, STA
• In 8085, Memory mapped I/O devices have 16 bit address.

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Differences between memory mapped I/O and isolated I/O –

ISOLATED I/O MEMORY MAPPED I/O

Memory and I/O have Both have same address
seperate address space space
Due to addition of I/O
All address can be used by the
addressable memory become
memory
less for memory
Separate instruction control
Same instructions can control
read and write operation in I/O
both I/O and Memory
and Memory
In this I/O address are called Normal memory address are
ports. for both
More efficient due to seperate
Lesser efficient
buses
Larger in size due to more
Smaller in size
buses
It is complex due to separate
Simpler logic is used as I/O is
separate logic is used to
also treated as memory only.
control both.

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Example of I/O Interface (I/O port)

Bidirectional Port A I/O Data

Data bus Bus buffer
register
Chip Select
Port B I/O Data

Internal bus
Register register
Timing
select
And Control Control
I/O Read control register
I/O Write
Status Status
register

To I/O CPU To I/O Devices

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 Example of I/O Interface (I/O port)
• Interface communicate with CPU though data
bus
• CS and RS determine interface address
• Set of 4 registers directly communicate with the
device
• I/O data can transfer port A or B
• Interface can use bidirectional lines when it is
connected to
– Input only (Character reader)
– Output only (Printer)
– Both (but not at the same time) (Hard disk)

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 Example of I/O Interface (I/O port)
• Issue commands – write command word to
control register
• Receive status – reading from status register
• Data transfer – via port A and B registers
• Function code of I/O bus not used
CS RS1 RS0 Register selected

0 X X None: data bus in high impedance

1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
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Asynchronous Data Transfer

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 Asynchronous Data Transfer
• Internal operations in a computer are
synchronize with internal clock pulse generator
– Applied to all registers
– All data transfer among registers happen at the same
time with the occurrence of the clock pulse
• But the CPU and I/O interfaces are independent
– They run on their own clocks
– If I/O shares common clock with CPU two units said
to be synchronize.
– Otherwise asynchronous
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 Asynchronous Data Transfer
• Asynchronous data transfer
– Requires control signals to indicate time at which transmission
occurs
• Main methods of indicate data transfer time
– Strobe - Giving a signal by one unit to indicate transfer time
– Handshaking - Transfer on agreement
• Data transfer with a control signal indicating the presence of data
• Data receiver sends an acknowledge receipt of data
• Timing diagrams are commonly used to show the
relationship between control signals
• Sequence of control signals depends whether transfer
initiated by source or destination

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 Strobe Control
• Uses a control line to time each transfer
• Strobe is activated either by source or
destination
• Strobe says when there is valid data on data bus
• Generally strobes activated by clock signals
• CPU is always in control of the transfer (i.e.
strobe is always from CPU)
• This method is mainly applicable in memory R/W
operations.
• Most of I/O operations use handshaking
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 Source initiated data transfer
• Source places data on the bus
• Have a brief delay to settle data on the bus
• Source activate the strobe pulse
• Then destination reads data to internal register (Often
uses falling edge)
• Source removes data after brief delay (Not necessary)
Data bus
Source Unit Strobe Destination Unit

Data Valid Data

Strobe

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 Destination initiated data transfer
• Initiated by destination
• Destination activates strobe
• Source places data on the bus
• Keeps data until accept them by destination
• Reads data to a register (Generally at falling edge of the strobe)
• Destination disable strobe
• Source removes data after predetermined time
Data bus
Source Unit Strobe Destination Unit

Data Valid Data

Strobe

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 Handshaking
• Strobe disadvantage
– In source initiation - Source doesn’t know
whether destination got the data
– In destination initiation – Destination doesn’t
know whether source has placed the data on
the bus
• Handshaking introduce a reply method to
solve this problem

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 Two wired handshaking
• 1st control line
– Same direction as the data flow
– Use by the source
– Indicates whether it has valid data
• 2nd control line
– From destination to source
– Uses by the destination
– Indicates whether it can accept data
• Sequence of control used depends on the unit initiate
transfer
• In a fault at one end timeout uses to detect the error

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Source Initiated Transfer
Data bus
Data valid Block
Source Unit Destination Unit Diagram
Data accepted

Data bus

Data valid Timing

Diagram

Data accepted

Place data on bus

Enable data valid Accept data from bus
Enable data accept
Sequence of
Disable data valid Initial stage events
Invalidate data on bus Disable data accepted
Ready to accept data 29
 Destination Initiated Transfer
Data bus
Data valid Block
Source Unit Destination Unit Diagram
Ready for data

Ready for data

Data valid Timing

Diagram

Data bus

Ready to accept data

Enable ready for data
Place data on bus
Enable data valid Sequence of
Accept data from bus events
Disable data valid Disable ready for data
Initial stage
Invalidate data on bus 30
 Asynchronous Serial Transfer
• Parallel transmission
– Each bit of message has its own path
– Total message transmitted at the same time
– N bit message requires N conduction paths
– Faster/expensive
– Short distance transmission
• Serial transmission
– Each bit in message sent in sequence one at a time
– Uses only one pair of conductors (or one conductor
with a common ground
– Slower/cheaper
– Uses for long distance transmission
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 Asynchronous Serial Transfer
• Synchronous
– Uses common clock frequency
– Transmits bits continuously
– For long distance transmission
• Use separate clocks with same frequency
• Keep clocks in step via synchronization signals send periodically
– Periodic synchronization signals should transfer even no data to
transmit
• Asynchronous
– Transmits only when data available to transmit
– Otherwise keeps in idle
– Uses start and stop bits at the both ends of the character code
– Transmission line rests at state 1 while idle
– Start bit is always 0
– Stop bit can be 1 or more 1s

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 Transmission Rules
1. When a character is not send line keeps in 1
state
2. Start of transmission of a bit is determined by
the start bit (usually 0)
3. Character bits always follows start bit
4. After the last character bit stop bit is detected
when the line returns to the state 1 for at least
one bit time

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 How it works
• Using transmission rules receiver detects start bit when
line goes 1 to 0
• Receiver knows
– Bit transmission rate
– Number of bits in character
• After a character transmission line keeps at state 1 for at
least one or two bits for resynchronization at both
transmitter and receiver
• Ex: Transmission rate 10 characters/sec (at 1 start bit, 8
info bits and 2 stop bits)  (1+8+2)*10 bit/s  110 bit/s
• i.e. baud rate  110 baud

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 Definitions
• Baud rate – Rate at which serial
information is transmitted and equivalent
to the data transfer in bits per second
• UART – Universal Asynchronous
Receiver-Transmitter (Asynchronous
Communication Interface)
– An interface which accept 8 bit character code
from a computer and forward corresponding
11 bit serial code to the device or does the
function other way around
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 Asynchronous Communication
Interface
Bidirectional
Data Bus Transmitter Transmit Data
Bus Buffer Shift Register
Register

Transmitter
Transmitter Clock
Chip Select CS Control Register
Internal Bus Control & clock

Register Select RS
Timing & Status Receiver Receiver Clock
Controlling Register Control & Clock
I/O Read RD

Receiver Receive Data

I/O Write WR Shift Register
Register

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 Asynchronous Communication
Interface
• Can function as both transmitter and receiver
• Initial mode is setup by control byte loaded to
control register
• CPU load and retrieve data via interface
registers while shift registers are used for data
serialization
• Register selection function shows bellow
CS RS Operation Register selected
0 X X None: data bus in high impedance
1 0 WR Transmitter Register
1 1 WR Control Register
1 0 RD Receiver register
1 1 RD Status register 37
 Operation
• Start by CPU by sending a byte to control
register specifying
– Mode of operation
– Baud rate to use
– Bits in each character
– No of stops bits should append
– Whether to use parity check
• Status register
– 2 bit Flags
• Transmit register is empty
• Receiver register is full

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 Operation
• Transmitter
– CPU reads status register
– Check flag to know whether transmit register is empty
– If empty CPU transfer character to transmit register & interface
marks register full
– Set 1st bit of shift register to 0, transfer character there and
append appropriate no of stop bits
– Mark transmit register empty
– Character is transmitted bit at a time in specified baud rate
– CPU can load another character after checking flag
– This is a double buffered interface, since new character can be
loaded as soon as previous one start transmission
• Receiver ?

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 Operation
• Receiver
– Receive data input line is in state 1 when line is idle
– Receiver controller monitors input line for occurrence of a 0
– Once start bit detected incoming bits of character are shifted to register
at prescribed baud rate
– Then it checks for parity and stop bits
– Character without start and stop bits transfer in parallel to the receiver
register
– Flag in status register set to indicate receiver register is full
– CPU checks flag and if data available read data and clears receiver
register full flag
• Possible receiving error
– Parity error – Failure in parity bit checking
– Framing error – Invalid stop bits
– Overrun error – Write next character before read previous by CPU

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Modes of Transfer

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 Modes of Transfer
• CPU merely execute instruction and accept data
temporally from I/O devices
• Ultimate source and destination is memory
– Receiving data from input devices  stores in
memory
– Sending data to output devices  from memory
• I/O handling modes
– Programmed I/O
– Interrupt-initiated I/O
– Direct Memory Access (DMA)

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 1. Programmed I/O
• I/O instructions are executed according to a program in CPU
• I/O instruction transfers from and to CPU registers
• A memory load instruction used to load it memory
• Another instruction used to verify data and count the number of
words transferred
• Constant I/O monitoring is required by CPU
• CPU stays in a program loop until I/O unit indicate data ready
• This waste CPU time

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 Programmed I/O – Input Device
Data bus
Data Register Data bus
Address bus
Interface
Data valid
CPU I/O Device
I/O Read
Status Data accepted
F
I/O Write Register

• I/O device and Interface use handshaking for data transfer

• Once data available on Data Register Interface sets flag bit (F)
indicating data availability
• Interface do not reset data accepted line until CPU reads data and
clear the flag
• CPU needs 3 instruction for each byte transfer
– Read the status register
– Check the flag bit
– Read data register when data available
• Transfer can be done in blocks for efficiency 44
Flow Chart For CPU Program To
Input Data
Read status register • Useful small low-speed
computers dedicate monitor
Check flag bit device continuously
=0
• Difference transfer rates between
Flag
CPU and I/O makes it inefficient
=1 • Ex:
Read data register
– Assumes a system read and check
flag in 1µs
Transfer data to memory
– Device transfer rate = 100
characters/s
Operation no
Complete
– i.e. 1 byte per 10000µs
yes   Only 1 transfer for 10000
checking
Continue
With
program 45
 2. Interrupt Initiated I/O
• Instead of continues monitoring at CPU interface
inform when data ready
• Uses interrupts
• CPU deviated from current program and take
care of data transfer
– Save return address from program counter to stack
– Then control branches to service routing
• Non vectored interrupts
• Vectored interrupts
• After completing I/O transfer it returns back to
previous program
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 Software Consideration
• In addition to h/w computer should have s/w
routings to control interface and transfer data
• Ex: Control commands – activate peripheral,
check data state, stop tape, print character,
issue interrupt
• I/O control software is fairly complex
• Standard I/O routing provided by the
manufacturer and included with OS
• I/O routings available as OS procedures; do not
need to go to assembly level details

47
 Priority Interrupts
• Generally I/O data transfer is initiated by CPU
• But device must be ready first
• Device readiness for data transfer can be identify by the
interrupt signal
• How CPU responds to the interrupt request
– Push return address to the memory stack
– Branch to the interrupt service routing
• Priority Interrupt system
– Deals with simultaneous interrupts and determine which one to
serve first (critical situation / fast I/O)
– Determine in which conditions allow interrupting while executing
another interrupt service routing

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 2.1 Polling (Software)
• Priority identification mechanism in software
• For all interrupts has a common branch address
• Then polls the interrupt devices in sequence
• The order at which it polls determine the priority
– Higher priority device is tested first.
– If its interrupt signal is on serves the device
– Then test for the next device
– Proceed on until last device
• Disadvantage: When there are multiple interrupts polling
time might exceed time available to service the I/O
device
• Solution: Hardware priority interrupts unit
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Hardware Priority Interrupt Units
• Accepts interrupts from many sources
• Determine which one has higher priority
• Issue interrupt accordingly to the CPU
• Further each interrupt source has its own
interrupt vector to access its own service routing
directly
• No polling required
• 2 major establishments of hardware priority
function
– Serial Connection (Daisy-chain)
– Parallel Connection

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 2.2 Daisy Chain
Priority data bus

VAD VAD VAD

PI Device1 P0 PI Device2 P0 PI Device3 P0
To Next
Device

INT
Interrupt request CPU
INTACK
Interrupt acknowledge

• Serial connection of all interrupt devices

• Higher priority one places first
• Interrupt request line is common (wired logic)
• CPU responds interrupt via Interrupt Acknowledge line
• If Device 1 has pending interrupt disable P1 and place its own
Interrupt vector. Otherwise pass it to the next device via P0

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 Parallel
Interrupt
Priority Interrupt
Register VAD
Disk I0 To CPU
Y
Printer I1 X
Priority 0
Reader I2 Encoder 0
0
Keyboard I3 0
0
0
IEN IST
Enable

Interrupt to CPU

INTACK from CPU

Mask 52
Register
 Parallel Priority Interrupt
• Uses a register to set interrupt bits by each
device
• Uses Mask Register change the sequence of
servicing
• Priority encoder generates Interrupt Vector
• CPU interrupt is generated only when
InterruptENable and InterruptSTate are set
• IEN can be set by the program
• With the INTACK from CPU VAD is put on to the
bus
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 Priority Encoder
• Implements the priority function

Inputs Outputs
Boolean function
I0 I1 I2 I3 x y IST

1 x x x 0 0 1
0 1 x x 0 1 1 x = I 0 ’ I 1’
0 0 1 x 1 0 1 x = I0’ I1 + I0’ I2’
0 0 0 1 1 1 1 (IST) = I0 + I1 + I2 + I3

0 0 0 0 1 1 0

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 Interrupt Cycle
• IEN uses by the program to enable or disable
interrupts while running
• At the end of each instruction cycle CPU checks
IEN and if enabled checks IST
• Sequence of micro operations follows as receive
an interrupt:
– SP  SP – 1
– M[SP]  PC
– INTACK  1
– PC  VAD
– IEN  0
– Go to fetch next instruction
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 Software Routing
• Priority interrupt system is a combination of Hardware
and Software techniques
• Computer has software routing to service interrupt
requests and to control interrupt hardware registers
I/O service program
Address KBD
Memory Program to service
0 JMP DISK Magnetic disk
1 JMP PTR
2 JMP RDR KBD
Program to service
3 JMP KBD
Line printer

Main Program KBD

750 Program to service
Character reader
Stack KBD
Program to service
256 256 Keyboard 56
750
 Initial and Final Operations
• Initial
– Clear lower-level mask register bits
– Clear interrupt status bit IST
– Save contents of processor registers
– Set interrupt enable bit IEN
– Proceed with service routine
• Final
– Clear interrupt enable bit IEN
– Restore contents of processor registers
– Clear the bit in the interrupt register belonging to the source that
have been serviced
– Set lower-level priority bits in the mask register
– Restore return address into PC and set IEN
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3. DMA (Direct Memory
Access)

58
 Direct Memory Access - DMA
• CPU limits the data transfer speed for fast I/O devices
• DMA removes CPU and allow peripherals to handle memory
bus
• During the transfer CPU does not have the control over the
bus
• CPU idling the bus can be done through the control signals
“Bus Request” & “Bus Grant”
– DMA controller enables BR,
– then CPU finishes current operation and puts its address and data
buses in high impedance
– CPU sets BG line
– DMA transfers data and resets BR for the CPU to use the memory
bus
• DMA data transfer can either happen as
– Burst transfer or
– Cycle stealing 59
 DMA Controller
Address bus

Data bus
Address bus buffers
buffer

Address Register

Internal bus
DMA select
Register select Word count register
Read
Write Control
logic Control register
Bus request
Bus grant DMA Request
Interrupt DMA Acknowledge To I/O device
60
 DMA Controller
• Interfaces with CPU and I/O devices
• Further DMA controller has
– Address Register – used for direct communication with memory
– Set of Address Lines – used for direct communication with memory
– Word Count Register – specifies the number of words to be
transferred
– Control register – Specifies the mode of transfer
• Data transfer is done directly between device and memory
under DMA control
• RD/WR signals are bidirectional
– When BG is set DMA can use them for memory RD/WR
– Otherwise CPU uses it DS and RS to write and read from DMA
• DMA uses Req and Ack signals with handshaking to
communicate with external peripheral devices
• CPU treat all DMA registers as I/O interface registers and
can be read and write under program control 61
 DMA Controller
• DMA is initialized by CPU
• Then DMA continues transfer an entire block of data
between memory and peripheral
• CPU sends following information on DMA initialization
– Starting address for memory read or write
– Word count the number of words to be transferred
– Control to specify mode of transfer
– Control to start transfer
• CPU communicates with DMA after transfer initialization
only if
– It receives an interrupt
– It wants to know how many words have been transferred

62
 DMA Transfer
• CPU communicates with DMA through
address and data bus as with any other
interface unit
• DMA has its own address by which DS &
RS activates
• CPU initialize DMA through data bus
• DMA can start data transfer between
memory and peripheral device as it gets
the control command
63
 DMA Transfer
Interrupt
Random-access
BG CPU
Memory (RAM)
BR

RD WR Address Data RD WR Address Data

Read Control
Write Control
Address bus
Data Bus

Address
select
RD WR Address Data
DS
Direct memory DMA Acknowledge
RS I/O
Access (DMA)
BR Peripheral
controller DMA Request
BG device
Interrupt
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 DMA Transfer - Sequence
• Peripheral device sends DMA request
• DMA controller activates BR
• CPU finishes current bus cycle and grant the bus by
activating BG
• DMA puts current address to the address bus and
activate RD or WR accordingly
• And acknowledges peripheral
• Then peripheral puts data to (or reads data from) the bus
• Thus peripheral directly read or write memory
• For each word transferred DMA increment address and
decrement word count register

65
 DMA Transfer – Sequence (Cont.)
• If word count is not zero DMA checks request line
coming from peripheral
– If active (fast devices) initiate the second transfer immediately
– Otherwise disable BR
• If word count is zero
– DMA stop transfer, disable BR and inform CPU the termination
of data transfer
• Zero value in word count indicates successful data
transfer
• DMA can have even more than one channel
• DMA commonly used in devices like magnetic disks and
screen display

66
 Types of DMA transfer using DMA controller
Burst Transfer :
DMA returns the bus after complete data transfer. A register is used as a byte count,
being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will
release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of the data
transfer.
Steps involved are:
1.Bus grant request time.
2.Transfer the entire block of data at transfer rate of device because the device is usually slow than the
speed at which the data can be transferred to CPU.
3.Release the control of the bus back to CPU
So, total time taken to transfer the N bytes
= Bus grant request time + (N) * (memory transfer rate) + Bus release control time.
Where, X µsec =data transfer time or preparation time (words/block) Y µsec =memory cycle time or cycle time or transfer
time (words/block) % CPU idle (Blocked)=(Y/X+Y)*100 % CPU Busy=(X/X+Y)*100
Cyclic Stealing :
In this DMA controller transfers one word at a time after which it must return the control of the buses to the CPU. The CPU merely delays
its operation for one memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle.
Steps Involved are:
1.Buffer the byte into the buffer
2.Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request)
3.Transfer the byte (at system bus speed)
4.Release the control of the bus back to CPU.
Before moving on transfer next byte of data, device performs step 1 again so that bus isn’t tied up and
the transfer won’t depend upon the transfer rate of device.
So, for 1 byte of transfer of data, time taken by using cycle stealing mode (T).
= time required for bus grant + 1 bus cycle to transfer data + time required to release the bus, it will be
NxT
In cycle stealing mode we always follow pipelining concept that when one byte is getting transferred then Device is parallel preparing the
next byte. “The fraction of CPU time to the data transfer time” if asked then cycle stealing mode is used.
Where, X µsec =data transfer time or preparation time (words/block) Y µsec =memory cycle time or cycle time or transfer
time (words/block) % CPU idle (Blocked) =(Y/X)*100 % CPU busy=(X/Y)*100

Interleaved mode: In this technique , the DMA controller takes over the system bus when the
microprocessor is not using it.An alternate half cycle i.e. half cycle DMA + half cycle processor.
67
I/O Processor (IOP)

68
 I/O Processing
• Instead of each interface communicating with the CPU
• One or more external processors assigned to communicate
directly with I/O devices
• IOP has both direct memory access and I/O communication
capabilities
• IOP releases the CPU from the housekeeping the chores
involved in I/O transfer
• Processors handling serial communication with remote
terminal are called Data Communication Processors (DCP)
• IOP is similar to CPU except its handles only I/O processing
• Unlike DMA controller totally setup by the CPU, IOP can
fetch and executes its own instructions
• Additionally IOP can perform other tasks like arithmetic,
logic, branching and code translation 69
Computer with I/O Processor

Central
processing unit
(CPU)

Memory bus
Memory unit Peripheral devices
PD PD PD PD

Input-output
Processor
I/O bus
(IOP)

70
 Responsibilities of IOP
• Memory at the centre can communicate with both
processors via DMA
• CPU responsible for data processing and computational
tasks
• IOP transfers data between peripheral devices and memory
• CPU is usually assigned the task of initiating the I/O
program, there after IOP operates independently
• IOP take care of data format difference and structure
mapping between memory and various I/O devices
• Communication between CPU and IOP is similar to
programmed I/O
• Communication between Memory and IOP is done as DMA
• IOP can be independent or slave processors depending on
the sophistication of the system
• Instructions for IOP generally refers as commands 71
 CPU-IOP Communication
Send instruction Transfer status word
To test IOP path To memory location

If status OK… send

Access memory for
Start I/O instruction
IOP program
To IOP
CPU Operations

IOP Operations
Conduct I/O transfers
CPU continues with
Using DMA; prepare
Another program
Status report

I/O transfer completed;

Request IOP status
Interrupt CPU

Check status word Transfer status word

For correct transfer To memory location
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