Buses in Assembly Language

Buses are the electrical paths to exchange data from one place to another place.

Types

internal external

Data Control Address

 Communication Modes:

Simplex:

Mobile Network
Sender Receiver

Human
Data Flow only in one Direction
i.e. only one sender and one receiver
 Send, Received
Communication Modes:

Half Duplex Mode:

Sender, Receiver Sender, Receiver

Human 1 Human 2
Send, Received

Data Flow in both direction but not at same time

i.e. each station can both transmit and receive, when send then not receive
 Send, Received
Communication Modes:

Full Duplex Mode:

Sender, Receiver Sender, Receiver

Human 1 Human 2
Send, Received

Data Flow can be transmitted in both directions on same time

i.e. each station can both send and receive
 Buses in Assembly Language

Buses are the electrical paths to exchange data from one place to another place.

Types

internal external

Data Control Address

Processor RAM I/O

 Buses in Assembly Language

Buses are the electrical paths to exchange data from one place to another place.

Types Two Operations in RAM

Read/Write

--Processor used the Control Bus to tell the RAM

Either its write or Read the data
internal external
--Processor used the Address Bus to tell the RAM
From where the data read

--Data bus pass the data from RAM to Processor

Data Control Address
Half Duplex Simplex Mode Status Msg
Read, Write 100 Error Msg
100
102
Processor RAM 104
106
108
--Address is always generated by CPU
 Communication Modes:
 The Address Bus
Unidirectional bus: Information transfer takes place in only one direction, from the
microprocessor to the memory or I/O elements.

 The data bus,

bidirectional bus: data can flow in both directions, that is, to or from the
microprocessor.

 The control bus

consists of a number of signals that are used to synchronize operation of the individual
microcomputer elements.

Is it Unidirectional or bidirectional bus ??

 Registers
High Level Language
Compiler

Assembly Code Assembler

Library Files Object File (Contain Source code)

Linker Machine Code

Hardware
 Registers

Address Bar

Processing Elements
Data Bus

Main Memory
Control Bus
Registers

CPU
 Registers
CPU
Why?
Optimization of Processing Time
Understanding of Hardware and Software interaction.

Hard Disk RAM Cache Registers

What?
Fastest Storage Area/location
“Quickly accessible by CPU as they
are built in to CPU” Registers are Built in memory inside the
CPU and access any data (i.e. stored in
Registers) very fast.

If we direct access the Registers to store

& access the data, our processing time
optimize. We can directly access the
Register in Assembly language.
Why should we learn Assembly Language?
1. Better/deep understanding of software and hardware interaction
2. Optimization of processing time
3. Embedded Programming
4. Course requirement

What is Assembly Language?

5. Computer Programming Language
6. Low level Programming Language
7. It uses Mnemonics/keywords
 Registers
What’s the origin of Registers?

Intel 4004 in 1971, Federico Faggin

Why he choose name Registers?

“Means Record or Collection of Information”

Just like the school note book which is used to store the lecture data…
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
1- Accumulator Register ax
Low
10101010 10101010
High X= Extended to 16 bits
E= Extended to 32 bits
R= Rich register to 64 bits
a, ax, eax, rax

Working of Accumulator Register?

It gives input and output (treat like and entrance door of home….) input/output operations
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
2- Base Register ax
Low
bh bl
10101010 10101010 bx
High
X= Extended to 16 bits
E= Extended to 32 bits
R= Rich register to 64 bits
b, bx, ebx, rbx
Working of Base Register?
Hold the starting addresses of data which are stored in RAM
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
3- Counter Register ax
Low
bh bl
10101010 10101010 bx
High
X= Extended to 16 bits cx ch cl
E= Extended to 32 bits
R= Rich register to 64 bits
c, cx, ecx, rcx
Working of Counter Register?
Counts the program running. Used in loops how many time’s program run…
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
4- Data Register ax
Low
bh bl
10101010 10101010 General purpose bx
High Registers
X= Extended to 16 bits cx ch cl
E= Extended to 32 bits
dh dl
R= Rich register to 64 bits dx
d, dx, edx, rdx
Working of Data Register?
Very important… it’s the final register which holds the data for output
which are going to print on computer Screen with the help of Accumulator Register
General Purpose Registers: These are the General Purpose registers because these are used for
different purpose not only one specific purpose. Input/output/addresses/holds the data/count the program….etc…
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
5- Code Segment ax

• These are the different type of registers and not used bh bl

General purpose bx
from user side.
• They are not divided like generalRegisters
purpose Registers.
• Naming convention remain same i.e. cs. cx ch cl
• Every type of architecture 8 bit, 16 bit, 32 bit or 64 bit,
we use cs convention. dh dl
Working of Code Segment dx

cs
• Program code are written in this section.
• When program is store in RAM it will hold the address of
the Memory where code segment is stored.
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
6- Data Segment ax

• These are the different type of registers and not used bh bl

General purpose bx
from user side.
• They are not divided like generalRegisters
purpose Registers.
• Naming convention remain same i.e. ds. cx ch cl
• Every type of architecture 8 bit, 16 bit, 32 bit or 64 bit,
we use ds convention. dh dl
Working of Code Segment dx

cs
• Program data are written in this section.
• When program is store in RAM it will hold the address of ds
the Memory where data of program is stored.
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
7- Stack Segment ax

• These are the different type of registers and not used bh bl

General purpose bx
from user side.
• They are not divided like generalRegisters
purpose Registers.
• Naming convention remain same i.e. ss. cx ch cl
• Every type of architecture 8 bit, 16 bit, 32 bit or 64 bit,
we use ds convention. dh dl
Working of Code Segment dx

cs
• It controls the memory management.
• It controls which data is enter in RAM first and which ds
data will out first. ss
• It hold the address of data which are load in memory.
e.g. of Stack FILO
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
8- Extra Segment ax

• These are the different type of registers and not used bh bl

General purpose bx
from user side.
• They are not divided like generalRegisters
purpose Registers.
• Naming convention remain same i.e. es. cx ch cl
• Every type of architecture 8 bit, 16 bit, 32 bit or 64 bit,
we use ds convention. dh dl
Working of Extra Segment dx

cs
• When your code segment area is full then extra segment is used.
• It create the separate area in RAM where the code is written and ds
Segment
the address of that area store in this segment. Registers ss
• It will hold the address of that code segment area which is extra es
created when first one is full.
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
9- Source Index ax

• These are the different type of registers and not used bh bl

General purpose bx
from user side.
• They are not divided like generalRegisters
purpose Registers.
• Naming convention remain same i.e. si. cx ch cl
• Every type of architecture 8 bit, 16 bit, 32 bit or 64 bit,
we use ds convention. dh dl
Working of Source Index dx

• It point the source operands. cs

• e.g. ds
Add dl, bl Segment
Registers ss
• Destination Source es
si
Add 3, bl
 Types of Registers
CPU
There are 14 types of registers. Eax Rax a
Q.? Why 14 types of registers? Why not 1? ah al
9- Source Index ax
Working of Source Index
bh bl
General purpose bx
Registers
• It point the source operands.
• e.g. cx ch cl
Add dl, bl
dh dl
• Destination Source dx

cs
Add 3, bl
Question? How CPU knows which one is either source or ds
Segment
destination Registers ss
Answer: Index
10- Destination es
Index si
• It points the destination operands. Registers di
 Types of Registers
CPU
There are 14 types of registers.
Q.? Why 14 types of registers? Why not 1? cs
Segment ds
11- Instruction Pointer
Registers ss
es

Working of Instruction Pointer

Index si
Registers di
Naming convention is same ip
It holds the address of the next instruction which will process. ip

e.g. Add dl, bl (This instruction is process now)

Add 3, bl IP hold the address of this line when

this line will process

Add bl, 3 then IP hold the address of this line)

 Types of Registers
CPU
There are 14 types of registers.
Q.? Why 14 types of registers? Why not 1? cs
Segment ds
12- Stack Pointer
Registers ss
es

Working of Stack Pointer

Index si
Registers di
top convention is same sp
Naming Stack
It point the current top of stack. Special Purpose ip
Registers sp
 Types of Registers
CPU
There are 14 types of registers.
Q.? Why 14 types of registers? Why not 1? cs
Segment ds
13- Flag Register
Registers ss
es

Working of Flag Register

Index si
Registers di
Naming convention is same f
It hold the current status of the program. Special Purpose ip
1 Registers sp
e.g. 1
1
0 f
The carry of this addition is store in flag Register because this is
the current status of the program.
 Types of Registers
CPU
There are 14 types of registers.
Q.? Why 14 types of registers? Why not 1? cs
Segment ds
14- Base Pointer
Registers ss
es

Working of Base Pointer

Index si
Registers di
Naming convention is same bp top Stack
It points base of the top of stack Special Purpose ip
Registers sp

f
bp
It Point this one