Writing Engineering Abstracts(33)

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(1 of 2)
(+) Logic circuits can achieve
optimization by full custom design flow, i.e. manual design
and layout, thus enhancing product performance and
lowering costs more than that achieved by the design flow
of hardware description language (HDL). Conversely, a
larger logic ASIC includes more than 1,000,000 gates in a
chip, which is difficult for full custom design to implement.
For a larger ASIC, full custom design flow requires
additional personnel, making it extremely difficult to achieve
time to market delivery. Therefore, this work describes
a novel HDL-based scheme for designing logic circuits,
capable not only of re-use as an IP in different processes,
but also of automatic regeneration of physical circuits.
(2 of 2)
All logic circuits are described by program editing. The
programs are then synthesized to gate level formats. Next,
all gates are placed and routed by auto-place-and-route
(APR) software to physical layered circuits. Additionally,
simulation parameters are estimated from APR software.
Moreover, the APR results are confirmed via simulation
that includes the processed parameters. Furthermore, all
description programs are re-used.
Simulation results indicate that, in addition to automatically
generating production via software, the proposed HDL-
based scheme decreases personnel by 50% for the same
IP procedure and accelerate market to time delivery.
Importantly, automatic design flow of the
proposed scheme avoids manually controlled errors,
ultimately increasing product throughput and reducing
personnel.
(1 of 2)
(+) Devi ce mi s-matchi ng
always complicates circuitry design owing to the inability to
identify the origin, thus accentuating the importance of
process control. In practice, circuit designers must add an
increasing number of devices in the circuitry to overcome
process deviation. For instance, mis-matching can
generate a yield loss of 20-30%. Whereas a larger chip
size implies a higher product price, a higher retail price
lowers market competitiveness. Therefore, this study
investigates the correlation between process parameters
and product yield.
(2 of 2)
By adopting the statistical process control (SPC)
method, process parameters are collected from the in-line
WIP. Major process-related factors are then identified using
correlation analysis. Next, the product yield is verified
based on these factors. Additionally, these process
parameters are stringently controlled to decrease the loss
of product yield. While analysis results
clarify the correlation between process parameters and
product yield, circuitry designers can focus on incorporating
the above factors without increasing device size,
ultimately reducing the chip area and lowering
the retail price.
Further details can be found at
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