Computer Architecture

• Introduction to CA
• Role of CA in designs
• Performance Issues
• Now … Review of some DLD Concepts
 Gate Level Components
Name Symbol VHDL Equation Truth Table
A X X <= A and B A B X
AND B
0 0 0
0 1 0
1 0 0
1 1 1
A X X <= A or B A B X
OR B
0 0 0
0 1 1
1 0 1
1 1 1

NOT A X X <= not A A X

0 1
1 0
 Composite Gates
A X X <= not (A and B) A B X
NAND B
0 0 1
0 1 1
1 0 1
1 1 0
A X A B X
NOR B X <= not (A or B)
0 0 1
0 1 0
1 0 0
1 1 0

A X X <= A xor B A B X
XOR B
0 0 0
0 1 1
1 0 1
1 1 0
 Boolean Algebra
• Logic -> Truth value of set of statements
• Algebra -> Mathematical Manipulation of
set of statements
• Boolean Algebra
• 0, 1, OR, NOT
• AND, IMPLICATION
 Definitions
• Associativity
• Commutativity
• Complement
• Idempotency
• De Morgan’s
 Logic Simplification

Two basic methods:

Boolean Algebra
Complicated
Accident Prone
Only way when the number of variables > 5

Karnaugh Map
Graphical - Pictorial
Simple when the number of variables <= 5
 Map Simplification
B BC
A 0 1 00 01 11 10
A
0 (A,B) (A,B)
0 (A,B,C) (A,B,C) (A,B,C) (A,B,C)
=0 =1 =0 =1 =3 =2
1 (A,B) (A,B)
1 (A,B,C) (A,B,C) (A,B,C) (A,B,C)
=2 =3 =4 =5 =7 =6

CD
AB 00 01 11 10
00 (A,B,C,D) (A,B,C,D) (A,B,C,D) (A,B,C,D)
=0 =1 =3 =2
01 (A,B,C,D) (A,B,C,D) (A,B,C,D) (A,B,C,D)
=4 =5 =7 =6
(A,B,C,D) (A,B,C,D) (A,B,C,D) (A,B,C,D)
11 = 12 = 13 = 15 = 14
(A,B,C,D) (A,B,C,D) (A,B,C,D) (A,B,C,D)
10 = 8 =9 = 11 = 10
 Map Simplification Example
A B C D X CD
0 0 0 0 0 AB 00 01 11 10
0 0 0 1 1
00
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 01
0 1 0 1 0
0 1 1 0 1 11
0 1 1 1 1
1 0 0 0 0 10
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

=> X = sum(1,2,3,6,7,9,10,11,12,15)
 Circuits
• Combinational Circuits
– For given Inputs, Unique Output
– Memory less, No Feedback
– Propagation Delay <-> Input to Output
• Sequential Circuits
– Maintains a “State”
– Output dependent on Inputs and State
– Time Dependent Behavior
Combinatorial Circuit Example- Half-adder

Half-adder has no Carry-in input

Function table:
A B Sum Carry-out
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logic diagram:

VHDL Code:
HALF_ADDER: process (A,B)
A Sum begin
B
Sum <= A xor B;
Carry_out <= A and B;
Carry-out
end process HALF_ADDER;
Combinatorial Circuit Example- Full-adder

Full-adder has a Carry-in input

Function table:

Carry-in A B Sum Carry-out

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Combinatorial Circuit Example- Full-adder
Logic diagram:

A
B

CI Sum

Carry-out

VHDL Code:

FULL_ADDER: process (A,B)

begin
Sum <= A xor B xor Carry-in;
Carry_out <= (A and B) or ((A xor B) and Carry_in);
end process FULL_ADDER;
Combinatorial Circuit Example- Decoder
n inputs and 2n outputs

Function table:

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
Combinatorial Circuit Example- Decoder
VHDL Code:

DECODER : process ( I(2 downto 0) )

begin
Y(7 downto 0) <= others => ‘0’;
case ( I(2 downto 0) ) is
when “000” => Y(0) <= ‘1’;
when “001” => Y(1) <= ‘1’;
when “010” => Y(2) <= ‘1’;
when “011” => Y(3) <= ‘1’;
when “100” => Y(4) <= ‘1’;
when “101” => Y(5) <= ‘1’;
when “110” => Y(6) <= ‘1’;
when “111” => Y(7) <= ‘1’;
end case;
end process DECODER;
Combinatorial Circuit Example- Encoder
2n Inputs and ‘n’ Outputs

Function table:

I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
Combinatorial Circuit Example- Encoder
VHDL Code:

ENCODER : process ( I(7 downto 0) )

begin
case ( I(7 downto 0) ) is
when “00000001” => Y <= “000”;
when “00000010” => Y <= “001”;
when “00000100” => Y <= “010”;
when “00001000” => Y <= “011”;
when “00010000” => Y <= “100”;
when “00100000” => Y <= “101”;
when “01000000” => Y <= “110”;
when “10000000” => Y <= “111”;
end case;
end process ENCODER;
 Combinatorial Circuit Example- Multiplexer
• Multiple Inputs , Control Input and One Output
• To select one of many inputs as Output
• N-to-1 MUX has ‘N’ Inputs and ‘1’ Output
• N is typically power of ‘2’
• Number of Control Inputs log2N
Combinatorial Circuit Example- Multiplexer
VHDL Code:

MULTIPLEXER : process ( S(1 downto 0) )

begin
case ( S(2 downto 0) ) is
when “00” => Y <= I(0);
when “01” => Y <= I(1);
when “10” => Y <= I(2);
when “11” => Y <= I(3);
end case;
end process MULTIPLEXER;
 Flip-Flops

Flip-flops are the most basic of sequential (clocked) circuits

Inputs are only considered valid during a clock edge transition

==> Inputs must be held stable during the transition

(called setup and hold interval)

Outputs only change after a clock edge transition

==> Outputs change after an interval called the

clock-to-output time
 Flip-Flop Types - SR

SR flip-flops have two inputs, set and reset, that act as follows:

Truth Table (set dominant):

S R C Q
x x 0 Q_last
x x 1 Q_last
1 x 1
0 1 0

Truth Table (reset dominant):

S R C Q
x x 0 Q_last
x x 1 Q_last
1 0 1
x 1 0
 Flip-Flop Types - SR

Symbolic representation: VHDL code (set dominant):

SR_FF : process (C)

S Q
begin
R if (C’event and (C = ‘1’)) then
if (S = ‘1’) then
C Q <= ‘1’;
elsif (R = ‘1’) then
Q <= ‘0’;
else
Q <= Q_last;
end if;
end if;
end process SR_FF;

Q_last <= Q;
 Flip-Flop Types - JK

JK flip-flops have two inputs, that act as follows:

Truth Table:
J K C Q
x x 0 Q_last
x x 1 Q_last
0 0 Q_last
0 1 0
1 0 1
1 1 /Q_last
 Flip-Flop Types - JK
Symbolic representation: VHDL code:
JK_FF : process (C)
begin
J Q if (C’event and (C = ‘1’)) then
K if ((J = ‘0’) and (K = ‘0’)) then
Q <= Q_last;
C elsif ((J = ‘1’) and (K = ‘0’)) then
Q <= ‘1’;
elsif ((J = ‘0’) and (K = ‘1’)) then
Q <= ‘0’;
else
Q <= not Q_last;
end if;
end if;
end process JK_FF;
Q_last <= Q;
 Flip-Flop Types - D
D flip-flops have one input, data, that act as follows:

Truth Table:
D C Q
x 0 Q_last
x 1 Q_last
0 0
1 1
 Flip-Flop Types - D

Symbolic representation: VHDL code:

D Q D_FF : process (C)

begin
if (C’event and (C = ‘1’)) then
C Q <= D;
end if;
end process D_FF;
 Flip-Flop Types - T

T flip-flops have one input, toggle, that act as follows:

Truth Table:
T C Q
x 0 Q_last
x 1 Q_last
0 Q_last
1 / Q_last
 Flip-Flop Types - T

Symbolic representation: VHDL code:

T Q T_FF : process (C)

begin
if (C’event and (C = ‘1’)) then
C if (T = ‘1’) then
Q <= not Q_last;
else
Q <= Q_last;
end if;
end process T_FF;

Q_last <= Q;
 Registers

Groups of D-type flip-flops, with each FF holding 1 bit of information

==> A 32-bit register would require 32 FF’s to implement

Registers can be loaded:

In parallel -- all bits at once
In serial -- one bit at a time, from either end

Registers are used to:

Temporarily store information for arithmetic operations
Implement control functions -- sets, resets, enables, etc.
Report status -- overflows, error conditions, etc.
Implement interrupts
 Registers- Parallel Load
Symbolic representation: VHDL code:

REGISTER : process (C)

D(n-1..0)
begin
Q(n-1..0) if (C’event and (C = ‘1’)) then
LOAD if (LOAD = ‘1’) then
Q <= D;
C else
Q <= Q_last;
end if;
Truth table: end process REGISTER;

LOAD C Q Q_last <= Q;

x 0 Q_last
x 1 Q_last
0 Q_last
1 D
 Registers- Serial Load (Shift)
Symbolic representation:

D
Q(n-1..0)
SHIFT

Truth table:

SHIFT C Q(0) Q(n-1..1)

x 0 Q_last(0) Q_last(n-1..1)
x 1 Q_last(0) Q_last(n-1..1)
0 Q_last(0) Q_last(n-1..1)
1 D Q_last(n-2..0)
 Registers- Serial Load (Shift)

VHDL code (8-bit register, for example):

REGISTER : process (C)

begin
if (C’event and (C = ‘1’)) then
if (SHIFT = ‘1’) then
Q (7 downto 1) <= Q_last (6 downto 0);
Q (0) <= D;
else
Q <= Q_last;
end if;
end process REGISTER;

Q_last <= Q;
 Counters

A counter is a register capable of incrementing or decrementing

its contents
Q <= Q plus n
Q <= Q minus n

The definition of "plus" and "minus" depend on the way the

register contents encode the integers

Binary Counters: Encode the integers with the binary number

code
Counters - Example: 3-bit Binary Up Counter
Truth Table: Symbolic Representation
CNT C Q_last Q
x 0 xxx Q_last Q(2..0)
x 1 xxx Q_last
0 xxx Q_last CNT
1 000 Q_last+1
1 ... Q_last+1 C
1 110 Q_last+1
1 111 000

State Diagram:
CNT
CNT CNT
001 010

000 011

CNT CNT

111 100

CNT
CNT 110 101
CNT
Counters - Example: 3-bit Binary Up Counter
Truth Table: Counter Design:
CNT C Q_last Q Bit Q(0) Toggles on every
x 0 xxx Q_last CNT = 1
x 1 xxx Q_last
0 xxx Q_last Bit Q(1) Toggles on every
1 000 Q_last+1 CNT = 1 and
1 ... Q_last+1 Q(0) = 1
1 110 Q_last+1
1 111 000 Bit Q(2) Toggles on every
CNT = 1 and
State Diagram: Q(0) = 1
CNT Q(1) = 1
CNT CNT
001 010

000 011

CNT CNT

111 100

CNT
CNT 110 101
CNT
Counters - Example: 3-bit Binary Up Counter
Logic Diagram (one design): Logic Diagram (another design):

CNT Q(0)
T Q CNT Q(0)
T Q

Q(1)
T Q Q(1)
T Q

Q(2)
T Q Q(2)
T Q
C
C

This is called series This is called parallel

(or ripple) carry logic (or look-ahead) carry logic
Counters - Example: 3-bit Binary Up Counter
VHDL Code:

COUNTER : process (C)

begin
if (C’event = (C = ‘1’)) then
if (CNT = ‘1’) then
if (Q_last = “111”) then
Q <= “000”;
Does this make ripple or
else
look-ahead carry logic?
Q <= Q_last + ‘1’;
end if;
end if;
end if;
end process COUNTER;

Q_last <= Q;
 Sequential Circuits

A sequential circuit which satisfies the following conditions:

There is at least one flip-flop in every loop

All flip-flops have the same type of dynamic clock

All clock inputs of all the flip-flops are driven by the

same clock signal.

Is called a synchronous sequential circuit

 Sequential Circuits

Any synchronous sequential circuit can be drawn in Canonical

form by pulling the flip-flops to the bottom of the figure (think of the
lines as elastic).

Since all loops have a flip-flop in them, this will leave the remaining
circuit without loops, and hence combinational.

Combinatorial Outputs This is called a

Logic Moore state
machine - outputs
depend only on
Inputs Combinatorial D Q State current state
Logic
C
 Sequential Circuits

Another way to design a state machine is a follows:

Combinatorial Outputs This is called a

Logic Mealy state
machine - outputs
depend on current
Inputs Combinatorial State state and inputs
D Q
Logic
C
 Sequential Circuit Descriptions

Structural
Logic diagram

Excitation Equations
Logical equations for the flip-flop inputs as a function
of current flip-flop states and circuit input signals

Output equations
Logical equations for circuit outputs as a function of
current flip-flop states and circuit inputs signals
 Sequential Circuit Descriptions
Behavioral
Transition and output equations
Logical equations for next flip-flop states and circuit
outputs in terms of current flip-flop states and circuit
input signals

Transition table
Two-dimensional truth table of transition and output
equations

State table
Transition table with the states given descriptive names

State diagram (graph)

A graph with nodes corresponding to states and
directed edges corresponding to state transistions
 Sequential Circuit Description- Example
Problem:
Build a 2-bit binary up/down counter, with the following I/O:
UP in : increment the count
DN in : decrement
Q(1..0) out : count

State diagram: VHDL Code:

 Sequential Circuit Description- Example

Transition Table: State Table:

UP DN Q Q_next UP DN Q Q_next
 Sequential Circuit Description- Example

Excitation Equation Q(1): Excitation Equation Q(0):

Q_next(1) = Q_next(0) =

Q(1..0) Q(1..0)
UP DN 00 01 11 10 UP DN 00 01 11 10
00 00

01 01

11 11

10 10
 Sequential Circuit Timing

The following global timing parameters are important to the reliable

working of a sequential circuit:

Global Setup and Hold: The window around any FF’s

clock edge during which its input must be valid

Global Clock-to-out: The amount of time that it takes to

get a signal, from the input clock, out of a circuit.

Maximum Clock Frequency: The fastest a global clock

can be run within a design.

Maximum Clock Skew: The greatest difference between

when a clock hits two different FF’s clock inputs
 Global Setup, Hold, &Propagation Delay

Consider the following circuit:

tPNI

D_ext Combinatorial D_int Output Net Q_ext

D Q Q_int
Logic Delay Delay
CLK_ext Clock Tree CLK_int tPNO
Network Delay
tPC tPFF
 Global Setup,Hold,&Propagation Delay
Consider the following timing diagram:

CLK_ext
tSU_E tHD_E

D_ext tSU_E = tSU_I + tPNI - tPC

tPNI tPC
tHD_E = tHD_I - tPNI + tPC
CLK_int
tSU_I tHD_I tP = tPC + tPFF + tPNO

D_int
tPFF

Q_int
tPNO

Q_ext
tP
 Maximum Clock Frequency

The maximum clock frequency, minimum clock width, is

determined by the time required for changes at one flip-flop output
to be seen at another flip-flop input.

Consider the following circuit:

tPFF tPN

D1 Q1 Combinatorial D2 Q2
D Q D Q
Logic Delay

Skew Between C1
Clocks

C1 tSKEW
 Maximum Clock Frequency
Consider the following timing diagram:

tPER

C1
tSKEW tSKEW
tPER = tPFF + tPN
C2
+ tSU + tSKEW
tPFF

Q1
tPN tSU

D2

Note the skewing C1 after C2 is the worst case. If the skew had delayed
C2 after C1, it would have increased the maximum clock
frequency.
 Maximum Clock Skew

Consider the same circuit as above:

tPFF tPN

D1 Q1 Combinatorial D2 Q2
D Q D Q
Logic Delay

Skew Between C1
Clocks

C1 tSKEW
 Maximum Clock Skew
Consider the same timing diagram as above:

C1
tSKEW tHD
tSKEW = tPFF + tPN - tHD
C2
tPFF

Q1
tPN

D2

Note the skewing C2 after C1 is the worst case. If the skew had
delayed C1 after C2, it would have increased the maximum clock
skew allowed.
 Summary
• Review of DLD
• Combinational & Sequential Circuits
• Basic Timing definitions in Circuits