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on
Custom VLSI Design Flow
Organized By
IETE Students Forum
ACE, Devsthali
Ambala
on
5th February, 2011
at
Electronics and Communication Engineering Department,
CONTENTS
Introduction to MOSFET
NMOS
PMOS
CMOS
Applied Research
Ambala College of Engineering and
Inverter Cross – Section
Fabrication
Theory
Mode of operation depends on Vg, Vd, Vs
+ +
Vgs = Vg – Vs Vgs Vgd
- -
Vgd = Vg – Vd Vs Vd
- +
Vds = Vd – Vs = Vgs - Vgd Vds
Theory
Approximate channel as connected to source
C = ε WL/t = C WL = C
gs ox ox ox permicronW
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, εox = 3.9ε0)
p-type body
4
3: CMOS Transistor
NMOS I-V SUMMARY
W
Theory
Shockley 1st order transistor models
β = µCox
L
0 Vgs < Vt cutoff
Vds V V < V
I ds = β Vgs − Vt − ds linear
2
ds dsat
β
( Vgs − Vt )
2
Vds > Vdsat saturation
2
5
Fabrication and Layout
NMOS OPERATION
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
0
n+ n+
S D
p bulk Si
6
Fabrication and Layout
PMOS TRANSISTOR
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
p+ p+
n bulk Si
7
Fabrication and Layout
TRANSISTORS AS SWITCHES
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to
g=0 g=1
drain
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
8
Fabrication and Layout
CMOS INVERTER
A Y VDD
0
1
A Y
A Y
GND Slid
e9
Fabrication and Layout
CMOS INVERTER
A Y VDD
0
1 0 OFF
A=1 Y=0
ON
A Y
GND Slid
e 10
Fabrication and Layout
CMOS INVERTER
A Y VDD
0 1
1 0 ON
A=0 Y=1
OFF
A Y
GND Slid
e 11
Fabrication and Layout
CMOS FABRICATION
CMOS transistors are fabricated on silicon
wafer
Lithography process similar to printing press
Slid
e 12
Fabrication and Layout
INVERTER CROSS-SECTION
Typically use p-type substrate for nMOS
transistor
Requires n-well for body of pMOS transistors
Several alternatives: SOI, twin-tub, etc.
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
Slid
e 13
Fabrication and Layout
WELL AND SUBSTRATE TAPS
Substrate must be tied to GND and n-well to
VDD
Metal to lightly-doped semiconductor forms
poor connection called Shottky Diode
Use heavily doped well
A and substrate
GND V
contacts / taps Y
DD
p+ n+ n+ p+ p+ n+
n well
p substrate
GND VDD
n-well
Polysilicon
n+ diffusion
Polysilicon
p+ diffusion
n+ Diffusion
Contact
Metal p+ Diffusion
Contact
Metal
Slid
e 16
Fabrication and Layout
FABRICATION STEPS
Start with blank wafer
Build inverter from the bottom up
p substrate
Slid
e 17
Fabrication and Layout
OXIDATION
Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate Slid
e 18
Fabrication and Layout
PHOTORESIST
Spin on photoresist
Photoresistis a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2
p substrate
Slid
e 19
Fabrication and Layout
LITHOGRAPHY
Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
Slid
e 20
Fabrication and Layout
ETCH
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been
exposed
Photoresist
SiO2
p substrate
Slid
e 21
Fabrication and Layout
STRIP PHOTORESIST
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
SiO2
p substrate
Slid
e 22
Fabrication and Layout
N-WELL
n-well is formed with diffusion or ion
implantation
Diffusion
Placewafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well
Slid
e 23
Fabrication and Layout
STRIP OXIDE
Strip off the remaining oxide using HF
Back to bare wafer with n-well
n well
p substrate Slid
e 24
Fabrication and Layout
POLYSILICON
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon
layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
Slid
e 25
Fabrication and Layout
POLYSILICON PATTERNING
Use same lithography process to pattern
polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
Slid
e 26
Fabrication and Layout
SELF-ALIGNED PROCESS
Use oxide and masking to expose where n+
dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-
well contact
n well
p substrate
Slid
e 27
Fabrication and Layout
N-DIFFUSION
Pattern oxide and form n+ regions
Self-aligned process where gate blocks
diffusion
Polysilicon is better than metal for self-
aligned gates because it doesn’t melt during
later processing
n+ Diffusion
n well
p substrate
Slid
e 28
Fabrication and Layout
N-DIFFUSION
Historically dopants were diffused
Usually ion implantation today
n+ n+ n+
n well
p substrate
Slid
e 29
Fabrication and Layout
N-DIFFUSION
Strip off oxide to complete patterning step
n+ n+ n+
n well
p substrate
Slid
e 30
Fabrication and Layout
P-DIFFUSION
Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
Slid
e 31
Fabrication and Layout
CONTACTS
Now we need to wire together the devices
Cover chip with thick field oxide
Contact
n well
p substrate
Slid
e 32
Fabrication and Layout
METALLIZATION
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving
wires
Metal
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
Slid
e 33
Fabrication and Layout
LAYOUT
Chips are specified with set of masks
Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
Feature size f = distance between source and
drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing
design rules
Express rules in terms of λ = f/2
E.g. λ = 0.3 µ m in 0.6 µ m process Slid
e 34
Fabrication and Layout
SIMPLIFIED DESIGN RULES
Conservative rules to get you started
Slid
e 35
INVERTER LAYOUT
Slid
e 36
Fabrication and Layout
SUMMARY
MOS Transistors are stack of gate, oxide,
silicon
Can be viewed as electrically controlled
switches
Build logic gates out of switches