Assembly Packaging Overview 2007 r2

Intel-USM
EBB526 Electronic Packaging

Chapter 2(a).
IC PACKAGE ASSEMBLY OVERVIEW
Rev 2
2007
May 07 © Intel Malaysia 2007

COURSE OBJECTIVES
At the end of this course, you will learn:
 The different types of assembly packaging
technologies
 The key process modules in assembly packaging
technologies
 The typical issues and challenges of the key process
modules
 Some solutions of the typical issues and challenges
of the key process modules
May 07 © Intel Malaysia 2007 2

COURSE OUTLINE
1. Assembly Packaging Overview
– Different Packaging Technologies and Process
Flow
– WB and Flip Chip Interconnection Technologies
– Ceramic and Plastic Package Technologies
2. Die Preparation
– Back-grinding
– Wafer Saw
– Issues and Challenges

COURSE OUTLINE
3. Chip Attach and 1st Level Interconnect
– Die Attach and Wire Bonding
– Flip Chip Attach and Deflux
4. Encapsulation
– Glob top encapsulation
– Molding
– Underfill

COURSE OUTLINE
5. Marking
– Laser Mark
– Ink Mark
6. Second Level Interconnect

– PGA, BGA, LGA
– Leaded and Lead-free
– Gravity and Positive Mask Ball Attach
Technologies

COURSE OUTLINE
7. Singulation
– Blade sawing
8. Media and Packing

– Processing Carriers
– Processing Trays
– Shipping Media (Tubes, Trays, Tapes and
reels, Boxes - inner and outer)

Section 1 :
Assembly Packaging Overview

ASSEMBLY PACKAGING OVERVIEW
 Examples of various package types
Dual In-line Zig-zag In-line Small Outline
Package (DIP) Package (ZIP) Package (SOP)
SSOP – Shrink Small
Outline
Package
TSOP – Thin Small
Quad Flat Quad Flat J-lead
Outline
Package
Package (QFP) Package (QFJ)
Land Grid Array Pin Grid Array Tape Carrier Transistor-

Package (LGA) Package (PGA) Package (TCP) outline (TO)

ASSEMBLY PACKAGING OVERVIEW
 Examples of various package types
Ball Grid Array Package (BGA)
– Wire bond technology
Ball Grid Array Package (BGA) Molded flip chip
– Flip Chip technology package
Thermally enhanced Thermally enhanced flip Wafer-level Chip Size

flip chip package chip package on interposer Package (W-CSP)

THE FUNCTIONS OF PACKAGE
1. Provide protection from mechanical, thermal,
chemical and any environment hazards
2. Dissipate heat
3. Distribute signal and power
4. Enable appropriate signal timing for desired
performance

Higher I/O
Higher EVOLUTION OF PACKAGE TECHNOLOGY
per package
I/O per area
package area
1960 1970 1980 1990 2000 2010

DIP
DIP QFP,
QFP, 1st
1st FC
FC WB
WB ceramic,
ceramic, TCP,
TCP, FC
FC Variants
Variants of
of DCA,
DCA, SOP,
SOP,
(IBM)
(IBM) WB ceramic,
ceramic, FC
FC FC,
FC, CSP,
CSP, SIP,
SIP,
WB plastic
plastic plastic WLP
SOC
SOC
plastic WLP

EVOLUTION OF PACKAGE TECHNOLOGY
BGA/
LEADLESS
CSP
Higher I/O density
BGA/LGA
PGA
Shrink DIP
TCP
LEADED
QFP
Skinny DIP
PLCC 
QFJ
ZIP TSOP
SSOP
SOJ
SOP
DIP
Smaller package size for same function
Courtesy of Prof. Rao R. Tummala
Director, Packaging Research Center and
Pettit Chair Professor,
May 07 © Intel Malaysia 2007 Georgia Institute of Technology 13
PACKAGING CLASSIFICATION
1. By mounting method
– Through hole mount packages (e.g. DIP, SIP, PGA)
– Surface mount packages (e.g. QFP, QFJ; PLCC)
– J lead, gull wing lead and butt lead
– Custom packages (e.g. TCP using TAB, IC card
package)
2. By first level interconnection technology
– Wire bonding technology packages (WB)
– Flip chip technology packages (FC)
– Tape-Automated bonding packages (TAB)

3. By integration of die, package, passive/active component
– Single die without package (e.g. DCA)
– Single die single package (e.g. QFP)
– Multiple die single package (e.g. MCM, SIP)
– Multiple unit (single die single package each) as single unit (e.g. POP)
– Embedded with passives & actives (e.g. SOP)
1 MCM
Package
Integration
SIP
3 Courtesy Ralf
Pleininger, Infineon
embedded actives
SOP & passives
Courtesy Ralf Pleininger, Infineon
4. By substrate material
– Hermetic ceramic, glass or metal* packages
– Non-hermetic plastic packages
– Ceramic is used as the conventional substrate material for high

performance and high I/O density products (1980s-now)
– Good CTE matching with silicon
– Good reliability even exposed to high temperature processing or
application condition
– Established technology
– Poor CTE matching with board if SMT second level interconnection is
used
– Organic substrate for high I/O is in new trend of industry (1990s-
now)
– Enable copper (Cu) metallization for better performance
– Lower cost
– Better CTE matching with board if SMT second level interconnection is
used
Note :
• Metal packaging has been eliminated from commercial products.
• Chip carrier = Quads

NUMBER OF LEADS REQUIRED
 Logic devices
– Rent’s Rule
Nleads =  Ngates
– Ngate is number of gates. Nleads is the number of leads.
–  and  coefficients vary with device type.
– Most accepted coefficients for microprocessors are
–  = 4.5 and  = 0.5.
– Example:
– 5000 gates require ~300 leads.
 Memory devices
Ncells = (2Nleads)
– Ncells is number of memory cells. Nleads is the number of
leads.
– Example:
– 256K = 218 (262,144)
– 256K DRAM should require 18 pins to access its memory cells. However
multiplexing is used to reduce access pins to 9, allowing a 16-pin DIP.

QUIZ : ASSEMBLY PACKAGING OVERVIEW
 List five typical package types.

 List two evolution trends of packaging
technology.
 Which are the four types of packaging
classification?
You are now ready to learn more details on

The typical assembly flow of Wire Bond
and Flip Chip technologies

WIRE BOND INTERCONNECTION
PACKAGING TECHNOLOGY
 Wire bond interconnection packaging

technology
– Uses aluminum or gold wire to connect the
silicon die to the substrate (first level
interconnection)
Second level Wire

Die
interconnection
pin Substrate

 Typical assembly process steps of the wire bond
interconnection packaging technology
Wafer Die
– Die preparation Tape Mounting wafer to tape
Frame
Sawing blade
Die sawing
Separated die
Lead Die attach
Gold preform Die attach frame paddle
– Die attaching or adhesive adhesive
droplets
Wire Wire
– Wire bonding
– ProtectionEncapsulation Lid Mold compound
ENCAPSULATION SEALING MOLDING

 Typical assembly process steps of the wire bond
interconnection packaging technology (continued…)
– Second level interconnect

Ball Attaching
– Marking
– Singulation Strip sawing
– Test & Inspection

reel-to-reel
– Packing or shipping tray

FLIP CHIP INTERCONNECT
 Flip Chip interconnection packaging

technology
– Uses controlled collapsed chip connection
(C4) solder bumps to connect the silicon die
to the substrate (first level interconnection)
Die
C4 bump Substrate
Second level interconnection ball

 Typical assembly process steps of the flip chip
Reflowing wafer
Wafer Die solder bumps
Frame
Sawing blade
Die sawing
Separated flip chip
Strip
– First level interconnect Solder Flip chip attaching
Mold compound
– Protection
UNDERFILL MOLDING
interconnection packaging technology (continued…)
– Second level interconnect

Ball Attaching
– Marking
– Singulation Strip sawing
– Test & Inspection

reel-to-reel
– Packing or shipping tray

TAPE AUTOMATED BONDING (TAB) INTERCONNECT
 Typical assembly process steps of the TAB
Reflowing wafer
Wafer Die solder bumps
Frame
Sawing blade
Die sawing
Gold bumps on
Tape
die or tape Flip chip attaching
– First level interconnect
Encapsulation
– Protection
GLOB TOP ENCAPSULATION

TAPE AUTOMATED BONDING (TAB) INTERCONNECT
(continued…)
–Marking
Trim and form (if needed)

–Singulation
–Test & Inspection reel-to-reel

or shipping tray
–Packing

CHALLENGES OF ASSEMBLY PACKAGING
 Assembly processes must be developed to meet various
expectations i.e.
– High product performance
– High product reliability
– Integrate silicon, package and board technologies
– Low cost
– Ease of manufacturing
– High yielding
– High productivity
 Products must be produced to meet the market requirements and
demand i.e.
– Form factor (miniaturization)
– Specific functions
– Performance [electrical and thermal e.g. I/O speed & bandwidth,
power (in and out), energy consumption, heat dissipation
technology]
– Different reliability use conditions
– Power consumption
– Environment friendly and legislative

QUIZ : ASSEMBLY PACKAGING OVERVIEW
 List one of the typical packaging assembly

process flows.
 What should the assembly processes be
developed for?
 Draw a package of any technology showing all
the key components of the package.

Die Preparation
Section 2 :
Die Preparation Module

Wafer Backgrind Process Overview
 Purpose
– The wafer backgrind process reduces the thickness of the wafer
produced by silicon fabrication (FAB) plant. The wash station
integrated into the same machine is used to wash away debris left
over from the grinding process.
Process Methods:
1) Coarse grinding
by mechanical
2) Fine polishing by
mechanical or
plasma etching
Method
The wafer is first mounted on a backgrind tape and is then loaded to the backgrind machine
coarse wheel. As the coarse grinding is completed, the wafer is transferred to a fine wheel for
polishing.

Wafer Backgrind Issues and Challenges
 Issues
– Ease of process
– Thin wafer handling from one step to another
– Backgrind tape removal
– Excessive stresses removal or reduction from the
wafer.
– Yield
– Wafer breakage due to stress built up during thinning
process.
– Scratches.
– Die metallization smearing.
– Equipment stability and capability
 Challenges
– Market requirements drive for very thin wafer (<3 mils)
– Flip chip wafer backgrinding

Wafer Separation Process Overview
 Purpose
– The wafer separation process is to divide the wafer into individual
dice or chips. Process Simulation of Saw Module
Process Simulation of Saw Module
Equipment
Equipment (mounting
(mounting not
not shown)
shown) Process Methods:
1) Sawing (with diamond-
impregnated saw blade)
• Single or dual cut
• Step cut or bevel cut
2) Partial scribing (with

laser beam, diamond-
tipped scribing tool, or
diamond-impregnated
Method saw blade)
The typical process is known as sawing or dicing. The wafer is first mounted on a frame and is
then loaded and carefully aligned through the consistent placement of the frame into the cutting
area. As the chuck table moves back and forth, one or two high-speed saw blades, plated with
nickel-diamond, cut across the wafer and part-way into the mounting tape. The wash station
integrated into the same machine is used to wash away debris left over from the cutting
process.
Wafer Sawing Process Overview
Wafer Sawing is a Front-of-Line (FOL) operation that cuts the wafer along the
streets separating the individual die. Streets, also called scribelines, are lines on
the wafer that separate each individual die from the surrounding dice. Kerf width is
the saw width. After the wafer is sawn, the wash station, using a detergent,
removes residual cut material from the wafer.

Wafer Sawing Issues and Challenges
 Issues
– Ease of process
– Die chipping control
– Multiple die types and sizes processing
– Yield
– Stringer
– Saw on die
– Scratches
– Chipping
– Die crack
 Challenges
– Smaller kerf width for more die per wafer
– Larger wafer size (300mm) with multiple die types and sizes

Flip Chip Wafer Reflow Process Overview
 Purpose
– If high lead bump is used, the flip chip wafer reflow process is
required to melt and form the FAB deposited C4 (Controlled
Collapsed Chip Connection) solder into a close-to-semi-sphere
(bump) shape for ease of chip attach processing.
Deposited Process Method:

Reflowed
solder bump
1) High temperature
H2 reduction
Metalization Metalization process
Silicon Silicon
Method
The bare wafers are loaded into a high temperature (400 oC) chamber with reducing atmosphere
(H2) with low oxygen ppm level. Temperature profile is programmed to remove the excessive
oxide from the tin lead bump to ease the flip chip attach process. A thin layer of oxide is later
formed during cool down to avoid oxidation of the bumps again.

SOLDER BUMP VOLUME APPROXIMATION
Solder
R
H Gold
 Nikel
Passivation
V =  / 6 x H x (H2 + 3 (D/2)2), or
V = (/24) x D3 x {[(cos  + 1) x (2 - cos )] / [sin  x (1 - cos )]}
Bump diameter 2R = (D2 + H2) / H

H = R + R cos  = [D x (1 + cos )] / 2 sin 

Flip Chip Wafer Reflow Issues and Challenges
 Issues
– Ease of process
– Oxidation control, uniformity of bumps
reflowing
– Yield
– Over oxidized
 Challenges
– Larger wafer reflow (300mm)

QUIZ : DIE PREPARATION
 What are the purposes of wafer backgrind,
wafer saw, and flip chip wafer reflow
processes, respectively?
 For each of wafer backgrind, wafer saw, and
flip chip wafer reflow processes, list
– Two process issues
– Two yield issues

Die/Chip Attach & First Level Interconnection
Section 3 :
Die / Chip Attach*
& 1st Level Interconnection
Modules
* Sometimes also called die bonding.

Die / Chip Attach Module
Flip Chip Technology Chip Attach Process Overview
 Purpose
– The flip-chip chip attach process is to sort the good dice and form
the first level interconnection by placing and joining the sawed die
in the right orientation accurately onto the substrate with solder
bumps reflowed to join the die to substrate.
Chip
Chip Attach
Attach Process
Process (without
(without Paste
Paste or
or DSC
DSC Attach)
Attach)
Process Methods:
1) Flux printing flip
chip attach
2) Die dipping flip
chip attach
3) Flux spraying flip
chip attach
Method
Eutectic bumps on the substrate or/and die are pre-applied by substrate supplier and FAB,
respectively. Flux is applied onto the substrate (to remove oxides and contamination). The
sawed die is then picked up from the wafer and flipped before it is placed on the substrate. The
die attached units are later sent for reflow furnace to melt the solder bumps to form the chip
joints. Molten solder self alignment characteristic helps to align the die to the substrate.
Flip Chip Technology Chip Attach Issues and Challenges
 Issues
– Ease of process
– Flux thickness control
– Cleaning of flux effectively Non-wet
– Yield
– Non-wet
– Die floating
 Challenges
– Market requirements drive for smaller die size with
tighter bump pitch and smaller bump size
– Lead free

Wire-Bond Technology Die Attach Process Overview
 Purpose
– The die attach process is to attach the sawed die in the right
orientation accurately onto the substrate with a bonding medium
in between to enable the next wire bond first level interconnection
operation.
Die attach adhesive
Dispenser
Pick tool Pressing and Process Methods:
holding scrubbing
Nozzle a die 1) Semi-automated
Die attach paddle eutectic die
attach
2) Fully automated
Input Dispense Die attach Output adhesive die
station station station station attach
Method
A bonding medium (silver-filled glass resins, organic adhesive, organic tape, or eutectic solder
e.g. gold preform) is first applied on the substrate die attach paddle and the sawed die is then
placed accurately onto the substrate with the bonding medium in between. Scrubbing may be
applied to spread the medium and improve bonding. Organic medium will then be cured.
(Gold preform die attach is only used for products that require very low backside resistance.)
Wire-Bond Technology Die Attach Issues and Challenges
 Issues Delamination
– Ease of process
– Bond line thickness control
– Void control
– Yield
– Adhesive on die
– Incomplete wetout/fillet Void
– Die crack
– Die placement
 Challenges
– Market requirements drive for very thin die (<3 mils)
– Material selection (e.g. lead free compatible, thermal
and electrical requirements)

First Level Interconnection Module
Wire Bond Process Overview
 Purpose
– The wire bond process is to form the interconnection between the
die and the substrate with wires welded on the die bond pads and
the substrate bond lead/fingers/pads.
Capillary Wire Package Process Methods:
shelf
Die 1) Gold ball bond
DA ( = 0.8-1.25 mils)
medium • Thermocompression
• Ultrasonic
• Thermosonic
2) Aluminum wedge bond
(less
conductive,  = 1.0-2.0
mils)
Method • Ultrasonic
For ball bonding process, a free air ball is first formed at the end of the wire by electronic flame-off
(EFO) firing. The ball is pulled up against the capillary and is bonded onto the die pad (first bond)
by force, temperature and ultrasonic energy. Capillary is then raised to form enough wire length
for the second bond . The wire is stitched on substrate finger/pad with a wedge-shaped
impression formed. The wire forms a looping profile that is programmable (to a certain extend).
Gold ball bond Aluminum wedge bond
Source:
OKI Silicon
Solutions
Company

• The WIRE BOND process is broken down into 5 major steps:
1. Units and Wire 3. Pattern Recognition
Load Objective: System (PRS) & Align
To load the carriers Objective:
with the die To recognize the
attached units alignment of the die
placed on them. and the package with
To load the wire their PRS eye points.
spool into the
machine.
2. Unit Preheat 4. Wire Bond
Objective: Objective:
To preheat the To weld wires onto
units for wire the die and the
bonding (ball bond substrate pads.
only).

• The WIRE BOND process is broken down into 5 major steps:
5. Unload
Objective:
To unload the
carriers after wire
bond.
To unload the wire
spool when the wire
is used up.

Wire Bond Issues and Challenges
 Issues Example: M-loop trajectory
– Ease of process
– Looping profile control
– Process optimization for bondability and bond reliability
– Yield
– Lifted bond (non stick on pad or lead)
– Sagging and swayed wire
– Tight loop
 Challenges
– Market requirements drive for tighter bond pitch (<37/75um
staggered, <60um non-staggered)
– Smaller wire diameter (<1.0mils)
– Brittle Intermetalic composition (IMC) on lead free

Tape Automated Bonding (TAB) Process Overview
 Purpose
– The TAB process is a batch interconnection method with an
etched metal frame fanout pattern on a film carrier to form the
interconnection between the substrate and the die on their
bonding pads.
Die
Tape finger
Bump Process Methods:

1) Thermocompression
Die without
bump Tape finger 2) Eutectic
Bump
Method
Solder bumps are deposited on the device pads to aid thermocompression bonding. Bumps can
also be etched onto leads of the tape rather than deposited on the device. The device is attached
on the tape with a simultaneous attachment of all the leads fingers to the chip bond pads. The
units are then heated to form the joints.
(Tape can be single, two or three layers.)

Tape Automated Bonding (TAB) Issues and Challenges
 Issues
– Ease of process
– Paddle shift control during molding
– Narrow spacing between leads retards the flow of molding compound
through the leads
– Non-uniform mold flow front below and above the tape induces stress
on the polyimide film and the fragile lead fingers thus deforms the
parts
– Single-layer copper tape not able to support longer thinner lead
fingers
– Single-layer electrically-continuous copper tape cannot be tested.
– Yield
– Attachment accuracy of large number of leads
– Opened bump joint due to insufficient bump solder on die pads or
lead fingers
 Challenges
– Stringent requirements on mold compound compatibility e.g. high
adhesion, low viscosity etc.
– Difficult in developing good low cost bumping technology.
– No wide acceptance due to accommodation of WB to electrical, thermal and
productivity needs.

QUIZ : CHIP ATTACH AND
1ST LEVEL INTERCONNECT
 What are the purposes of the die attach and
the first level interconnect processes?
 For each of wire-bond-technology die attach,
flip-chip chip attach, wire bonding, and tape
automated bonding processes, list

Encapsulation
Section 4 :
Glob Top Encapsulation / Mold /
Underfill / Sealing Module

Glob Top Encapsulation / Mold / Underfill / Sealing Module
Process Overview
 Purpose
– The encapsulation process is to form a protection to the die and
the first level interconnection from being damaged from handling,
moisture, dirt, heat, radiation, or other sources using a thermoset
material.
Process Methods:
1) Glob top encapsulation
2) Molding
3) Flip chip underfill
4) Hermetic lid sealing (for ceramic packages)
1) Glob Top Encapsulation Method
Die
Glob top encapsulation is applied on top of the die after the first level interconnection is formed.
Thermoset polymer is dispensed with a needle nozzle at a location or in a form of line(s) to cover
the entire die and the first level interconnection. The units are then sent for cure to achieve the
desired mechanical and moisture resistance properties of the encapsulation material.
Process Overview
2) Molding Method
Molding is applied by transfer pressure to flow on top or around the die and its first level
interconnection. Mold pellet is placed into the transfer pot and is soften at an elevated
temperature for a preset time before it is pushed by a plunger. The units are either cured in line or
sent for a separate cure oven to achieve the desired mechanical and moisture resistance
properties of the mold material.

Process Overview
3) Flip Chip Underfill Method
After the flip chip first level interconnection is completed, the parts are first dried/pre-baked to
remove moisture from the substrate and then pre-heated to a desired temperature, underfill epoxy
is later dispensed with a needle nozzle at a location or in a form of line(s) to allow the underfill
material to cover the entire die and the first level interconnection. The units are then sent for cure
to achieve the desired mechanical and moisture resistance properties of the encapsulation
material.

Process Overview
4) Sealing Method
After the first level interconnection is completed, a lid (either ceramic, metal pr plastic lids) with
solder printed on its peripheral is then placed to enclose the substrate cavity that has the wire
bonded die in it. The unit is then sent for reflow to have the solder molten and seal around the lid.

Glob Top Encapsulation Issues and Challenges
 Issues
– Ease of process
– Optimization of dispense weight and pattern for different form
factors.
– Avoid excessive interaction of process heat to the
encapsulation material (pot life).
– Yield
– Void or bubble.
– Drips on unit.
– Overflow of encapsulation material beyond the desired region.
– Foreign material (FM) / foreign particles.
 Challenges
– Tighter wire bond pitch can retard flow of encapsulation and trap
air and then form void or bubble.
– Laser marking on the glob top encapsulation surface can initiate
cracks.
– Thermal expansion compatibility to wire of smaller diameter.

Mold Issues and Challenges
 Issues
– Ease of process
– Wire sway due to the flow of molding compound.
– Post mold warping of strip or unit due to the flow-induced
stress.
– Yield
– Excess mold flash.
– Incomplete molding.
– Voids.
 Challenges
– Tighter bond pitch (<37/75um staggered, <60um non-
staggered) requires smaller filler size in molding compound.
– Smaller wire diameter (<1.0mils) which is more prone to
wire sway.
– Lead free compatible molding compound material.

Underfill Issues and Challenges
 Issues
– Ease of process
– Optimization of dispense weight and pattern.
– Fillet width control especially at the dispense side(s).
– Underfill voiding control.
– Avoid excessive interaction of process heat to the underfill
material (pot life).
– Yield
– Drips on unit.
– Underfill material on die.
– Incomplete filleting at opposite dispense side(s).
 Challenges
– Lead free compatible underfill material is expected.
– Tighter bump pitch requires smaller filler size in underfill material.
– Tighter bump pitch is more prone to void formation.

Sealing Issues and Challenges
 Issues
– Ease of process
– Optimization of lid solder pattern/profile, width and
height.
– Optimization of solder reflow profile.
– Yield
– Solder splashes.
– Test short due to free solder balling in cavity.
– Lid misplacement.
 Challenges
– Lead free compatible solder is expected.

QUIZ : Glob Top Encapsulation / Mold /
Underfill / Sealing Module
 What are the purposes of encapsulation?

 For each of glob top encapsulation, mold and
underfill processes, list

Marking
Section 5 :
Marking Module

Marking Module
Marking Process Overview
 Purpose
– To etch legible product identification data (device code, date of
manufacture, the manufacturer and the country of origin) on to the
package surface.
Process Methods:
1) Laser marking / writing
2) Polymer-based ink jetting
3) Polymer-based ink stamping
Method
For laser marking, trays of units are indexed under the laser, which burns the product name and
bin information onto the unit (die or substrate surface). Similar process is used for ink jetting with
the polymer-based ink except that ink is sprayed onto the unit surface. For ink stamping process,
a stamp is used to transfer ink from a ink pad to the unit surface.

Marking Module
Marking Issues and Challenges
 Issues
– Ease of process
– Optimization of the laser mark depth in avoiding
reliability impacts to the marked surface.
– Yield
– Legibility issue.
– Offset marking.
– Ink smearing.
 Challenges
– Smaller form factor with limited marking area.
– Laser marking on the glob top encapsulation
surface can initiate cracks.

QUIZ : GLOB TOP ENCAPSULATION /
MOLD / UNDERFILL MODULE
 What is the purpose of marking?
 List the below for marking process
– Two process methods

Second Level Interconnection
Section 6 :
Second Level Interconnection Module

Trim and Form Process Overview
 Purpose
– The second level interconnection process is to prepare the
interconnection structure on the units to form joints with the
board.
Process Methods:
1) Lead fingers (by trim-and-form)
2) Balls attach (by gravity or vacuum; flux or solder paste)
3) Lands (with or without solder)
4) Pins (butt pins, inserted pins)
1) Trim and Form Method
Butt-lead
J-lead
Gull-wing
Trim and punch operation is conducted in a punch in which a trim-and-form tool is mounted. It first
cut the copper frame that connect all the lead fingers. The lead fingers will then be formed to the
shape required. Leads are coated with solder with either solder dipping (after singulation) or
solder plating operation (before singulation).

Trim and Form Process Overview
 Issues
– Ease of process
– Coplanarity control of the finished units.
– Solder plating control to avoid excessive
thermal shock to the molded body.
– Yield
– Damaged or missing lead.
– Coplanarity reject.
 Challenges
– Maintaining coplanarity for larger packages.

Ball Attach Process Overview
2) Ball Attach method
In the vacuum ball attach method, flux is applied onto a flux table and spread to a thin, uniform
layer with a squeegee. The ball attach tooling picks up the balls with a vacuum, dips them into the
flux, and attaches them to the substrate lands. The ball tooling uses a patterned grid to place the
balls in the correct location on the lands. The flux cleans the lands, provides tack to hold the balls
in place prior to reflow and removes oxides from the ball surface for proper reflow.
In the gravity ball attach method, flux are printed directly on the packages following the patterned
grid. The balls are placed into a ball mask with holes of the same patterned grid. Once the
packages printed with flux are placed against the ball mask, the tooling will turn to a position to let
go of the balls with gravity effect and the balls are attached onto the package lands.

Ball Attach Issues and Challenges
 Issues
– Ease of process
– Control of flux amount.
– Different package types require different tooling and
setups.
– Yield
– Missing balls*.
– Merged balls*.
 Challenges
– Tighter ball pitch requires smaller ball size.
– Smaller ball size on large package is prone to solder joint
reliability issue.
Note : * Most yield losses are reworkable.

Land and Pin Process Overview
3) Land
No special package assembly process is needed if land is used as a second level interconnection
method for board assembly. Units are to be clamped with a spring loaded mechanism onto the
board for a direct contact (with or without solder on board).
4) Pin (insert or butt pin attach)
No special package assembly process is usually needed if pin is used as a second level
interconnection method for board assembly. Pins are usually attached (by inserting or soldering)
by the substrate supplier in the panel form for a more efficient pin attaching before substrate
singulation.

QUIZ : Second Level Interconnection Module
 What are the purposes of second level
interconnection?
 For each of trim-and-form and ball attach
methods, list

Singulation
Section 7 :
Singulation Module

Singulation Module
Singulation Process Overview
 Purpose
– The singulation process is to separate finished units from the
strips or tapes or lead frames.
Process Methods:
1) Punching 5) Laser cutting (Nd:YAG laser system)
2) Sawing / dicing 6) Bend and slap
3) Routing 7) Shearing
4) Pinching
1) Punching method
Punch singulation operation is conducted by mechanical shearing with the tooling made of high
speed steel material. A few units can be punched at one time.

Singulation Module
 Purpose
– The singulation process is to separate finished units from the
strips or tapes or lead frames.
Process Methods:
1) Punching 5) Laser cutting (Nd:YAG laser system)
2) Sawing / dicing 6) Bend and slap
3) Routing 7) Shearing
4) Pinching
1) Punching method
Punch singulation operation is conducted by mechanical shearing with the tooling made of high
speed steel material. A few units can be punched at one time.

Singulation Module
2) Saw Singulation method
The strips are first loaded into a saw station. The saw machine then separates the units with
sawing blades. Units will later be cleaned and picked up from the nest to a shipping tray.

Singulation Module
3) Routing method
Units (usually CSP) are singulated with a focused laser beam system while being moved on a
high speed* and high precision X-Y translation stage. A high-speed jet of gas is used to blow
away the debris and prevent excessive accumulation of heat to the CSP surface during the
singulation process. Not commonly used.
Routing bit Pinching
Source : FKN Systek, Inc

4) Pinching method
Units are singulated by pressure with the principle of circular blade on circular blade or circular
blade on linear blade operation along the remaining material of a scoreline. Not commonly used.

Singulation Module
5) Laser cutting method
Units (usually CSP) are singulated with a focused laser beam system while being moved on a
high speed* and high precision X-Y translation stage. A high-speed jet of gas is used to blow
away the debris and prevent excessive accumulation of heat to the CSP surface during the
singulation process. Not commonly used.
6) Bend and slap method

Developed to aid in the breaking of edge strips from scored and routed panels. Not commonly
used.
Bend and slap Shearing
Source : FKN Systek, Inc

7) Shearing method
A high stress method to singulate units. Not commercially available.
Note: * The laser cutting process is able to achieve 70 mm/s for packages with 1.1 mm
thickness.
Singulation Module
Punch Singulation Process Overview
 Issues
– Ease of process
– Punch tool life assessment.
– Optimization to process incoming warped strip.
– Optimization to have a smooth cutting edge.
– Yield
– Punch offset (X, Y).
– Chipping.
– Irregular edge.
 Challenges
– More I/O within same real estate calls for narrower ball to
edge gap.
– Larger die size affects incoming levelness.
– Thicker substrate or larger form factor is more difficult for
singulation.

QUIZ : Singulation Module
 What is the purpose of singulation?
 For the singulation methods, list

Section 8 :
Media and Packing Module

Media Overview
 Purpose
– MEDIA is used for in-line package assembly processing by
carrying usually the singulated parts or components.
Media Types:
1) Metal carrier
2) Plastic tray
3) Tape and reel
1) Metal carrier
Used to process parts at elevated temperature for a long period of time. Usually used in the
front-of-line assembly processes which involves polymer curing at high temperature. Metal
carrier is usually more expensive.
2) Plastic tray
Used to process parts at a lower temperature. Usually used in the end-of-line assembly
processes which does not involve processes at high temperature for a long time.
3) Tape and reel
Used to contain components such as singulated die or capacitors that are assembled onto the
substrate.

Packing Process Overview
 Purpose
– PACKING PROCESS is used to protect the finished parts from
damage due to moisture, handling and shipment.
Packing Types:
1) Individual packing (tubes, plastic tray, tape and reel)
2) Inner box (boxes, empty top and bottom cover trays, cartons,
moisture proof bags, with cushioning material)
3) Outer box (bigger boxes with cushioning material)
1) Individual packing
Units are kept in tubes, plastic tray or tape and reel separating each finished parts from others.
2) Inner box
Used to contain the tubes, plastic tray or tape and reel for an easier manual handling.
3) Outer box
Used to contain the inner boxes for shipment.

Packing Process Overview
 Typical packing process
Source:
OKI Silicon Solutions
Company

Media and Packing Process Overview
 Issues
– Ease of process
– Manual handling
– Yield
– Unit drop
 Challenges
– Heavy parts handling.

QUIZ : Media and Packing Module
 What are the purposes of media and packing?

 List one process issue and one yield issue of
packing.

References
 Louis T. Manzione, ‘Plastic Packaging of
Microelectronic Devices’, AT&T Bell Laboratories
Division, Van Nostrand Reinhold, New York.
 Ray P. Prasad, ‘Surface Mount Technology –
Principles and Practice’, Van Nostrand Reinhold, New
York.
 John H. Lau, ‘Low Cost Flip Chip Technologies’,
McGrraw-Hill.
 http://www.intel.com/technology/itj/archive.htm
 http://www.intel.com/research/silicon/packaging.htm
 http://www.okisemi.com/jp/english/package0.htm
 http://www.semiconfareast.com/index.html
 http://www.tpub.com/neets/book14/57f.htm
Back-up

• The BACKGRIND process is broken down into 8 steps:
3. Backgrind Tape
1. Load and Align lamination
To load and align To laminate a
the wafer into the protective layer of film
wafer cleaning and on the circuitry surface
tape lamination of the wafer.
machine.
2. Wafer cleaning 4. Coarse grinding
DI water
To clean the wafer To reduce the
for the next thickness with a
lamination step. coarse grinding wheel.

• The BACKGRIND process is broken down into 8 steps:
5. Fine polishing Objective: 7. Load

To eliminate or Objective:
DI water
reduce the stress To load the wafer to
built up during wafer mounter.
coarse grinding
and polish the
surface to remove
micro cracks with a
fine grinding wheel.
6. Unload 7. Tape removal
To unload the wafer To remove the
from backgrinding backgrind tape after
machine. wafer mounted on
the frame.

Wafer Sawing Process Overview
• The SAWING process is broken down into four steps:
Objective:
1. Load and Align 3. Cut
To separate dice from a
Objective: wafer with resin-
To load and align bonded diamond
the mounted wafer wheel. (First blade is
into the cutting area used to remove metal
in consistent structures and
placement. stresses on street for
second blade.)
2. Pattern Recognition 4. Wash, Rinse,
System (PRS) Dry and Unload
Objective:
Objective:
To rinse slurry (silicon
To align the theta
dust) before it dries
(rotation) position
with de-ionized water
of the wafer, so
and CO2. Also to dry
that the saw
blades cut parallel wafer by spinning and
to the streets. with clean air, and
unload wafer.
May 07
eyepoints © Intel Malaysia 2007 92
Wafer Reflow Process Overview
• The WAFER REFLOW process is broken down into 3 steps:
1. Load 3. Unload
To load the wafers To unload the
into the reflow oven wafers from the
or furnace. reflow oven or
furnace.
2. Wafer reflow
Objective:
To reflow the wafer
bumps and remove
the excessive
oxide.

• The FLIP CHIP DIE ATTACH process is broken down into 9 major steps:
1. Units and Dice/ 3. Pattern Recognition
wafer Load (DA) Objective: System (PRS) & Align
To load the carriers
with the units Objective:
placed on them. To align the theta
To load the sawed (rotation) and X-Y
wafer/dice into the position of the die
machine. and the package.
2. Screen Printing 4. Chip Placement
Objective:
To print the flux Objective:
onto the substrate To attach the flip chip
bump solder. onto the substrate.

5. Reflow 7. Load (Deflux)

To form the To load the carriers
interconnection into the deflux
between the die machine.
and the substrate.
6. Unload (Die
Attach) 8. Deflux
To unload the To remove flux
carriers after die residue in between
attach. the die and the
To unload the substrate. Units will
tape/wafer frame be dried after
when all good dice defluxing.
are picked up.
9. Unload (Deflux)
Objective:
To unload the carriers
from deflux machine.
Note: If needed for Die side capacitor (DSC) attach, solder paste is
applied to the chip capacitor lands on the substrate.

• The WIRE BOND DIE ATTACH process is broken down into 8 major steps:
1. Units and Dice/ 3. Pattern Recognition
wafer Load (DA) Objective: System (PRS) & Align

with the units To align the theta
placed on them. (rotation) position of
To load the the wafer. To align the
dice/wafer into the die (X-Y) with respect
machine. to the package PRS
eyepoints eye points.
2. Bonding Medium
Dispense 4. Die Attach
To dispense the To attach the die
bonding medium precisely and form a
onto the substrate good adhesion with
die attach paddle. desired bond line
thickness (BLT).

• The WIRE BOND DIE ATTACH process is broken down into 8 major steps:
5. Unload (Die
7. Cure
Attach) Objective: Objective:
To unload the To cure the die attach
carriers after die material to the
attach. desirable mechanical,
To unload the wafer thermal and electrical
frame when all good properties.
dice are picked up.
6. Load (Cure) 8. Unload (Cure)
To load the carriers To unload the carriers
into cure oven. from cure oven.
* Cure is needed only on adhesive die attach.

• The TBA process is broken down into 5 major steps:
1. Dice and Tape 3. Pattern Recognition
Load Objective: System (PRS) & Align
To load the sorted Objective:
die or wafer. To recognize the die
To load the tape and package
spool into the alignment with their
machine. PRS eyepoints.
2. Unit Preheat 4. Inner Lead Bonding
To preheat the tape To bond the die on
(thermocompression). the substrate with
pressure, heat and/or
ultrasonic.

• The TAB process is broken down into 5 major steps:
5. Unload
Objective:
To unload the chip
tape/wafer frame
when all good dice
are picked up.
To unload the TAB
tape spool when the
tape is used up.

Glob Top Encapsulation Process Overview
• The GLOB TOP ENCAPSULATION process is broken down into 8 major steps:
Step Objective
1. Units Load (Encap) To load the carriers with the units placed on them.
2. Units Preheat To preheat the chip-attached parts to a desired
temperature to ease the flow of encapsulation material
later.
3. Pattern Recognition To recognize the units’ X-Y, rotation position by
System (PRS) referring to the package PRS eye points for an
accurate dispensing.
4. Dispense material To dispense the encapsulation material on top of the
die or into the die cavity (for a pre-molded package).
5. Unload (Encap)* To unload the carriers after encapsulation.
6. Load (Cure)* To load the carriers into the cure oven.
7. Cure To cure the encapsulation material to the desirable
mechanical properties.
8. Unload (Cure) To unload the carriers from the cure oven.
* Dispense and cure can be linked if needed.
Mold Process Overview
• The MOLDING process is broken down into 16 major steps:
Step Objective
1. Load (Prebake) To load the units (in specially designed cassettes) into the
prebake oven (usually manually).
2. Prebake To remove residual moisture from the die and the package
that will react with the coupling agent in the mold compound,
causing random voids in the mold. Load/unload of the units
(in specially designed cassettes) are usually done manually.
3. Unload (Prebake) To unload the units from the prebake oven (usually manually).
4. Load (Plasma clean) To load the units (in specially designed cassettes) into the
plasma chamber (usually manually).
5. Plasma clean To clean the exposed surfaces of the die and the package in
order to improve the adhesion of the mold compound.
Load/unload of the units (in specially designed cassettes) are
usually done manually.
6. Unload (Plasma clean) To unload the units from the prebake oven (usually manually).

Step Objective
7. Load (Mold) To load (manually or automatically) the units onto the
lower mold half.
8. Positioning and To position the units onto the registration pins on the
clamping mold. The mold halves are then brought together into
the clamped position.
9. Mold compound To place the thermoset molding compound into the
preparation transfer pot of the molding tool for preheating.
10. Strip preheating To preheat the strip to ease molding.
11. Mold transfer, cure To transfer the molding compound into the mold
and unit separation runner system (by the plunger).
To cure the mold compound at a preset time.
To separate the individual units after cure (cull
breaking).
12. Unload To unload the units after molding.

Step Objective
13. Load (PMC) To load the units into the cure oven (usually manually).
14. Post mold cure To completely cure the mold compound for the
desirable mechanical properties.
15. Unload (PMC) To unload the units from the cure oven (usually
manually).
16. Deflashing / To remove the excess molding compound or the thin
Dejunking (if needed) flash of molding compound (known as resin bleed or
flash) from the strips.
(i. Media deflashers, ii. solvent deflashers and iii.
water deflashers)

Underfill Process Overview
• The UNDERFILL process is broken down into 10 major steps:
Step Objective
1. Load (Underfill) To load the chip-attached units into the prebake oven.
To load the underfill syringe into the dispenser.
2. Prebake* To remove the moisture absorbed in the package that
will cause random voids in the underfill.
3. Preheat To preheat the parts exited from the prebake oven to a
desired temperature to ease the flow of underfill
material later.
accurate dispensing.
5. Dispense material To dispense the underfill material at the side of the die.
6. Post-dispense To promote the capillary flow the underfill material to
heating cover the entire die area.
7. Unload (Underfill) To unload the carriers after underfill.
* Underfill is more sensitive to moisture and can form voids which affect the part reliability.
Prebake and dispense are usually linked to avoid extended exposure for moisture
absorption again after prebake.
Underfill Process Overview
8. Load (Cure)* To load the carriers into the cure oven.
9. Cure To cure the encapsulation material to the desirable
mechanical properties.
10. Unload (Cure) To unload the carriers from the cure oven.

Sealing Process Overview
• The SEALING process is broken down into 7 major steps:
Step Objective
1. Load (lid attach) To load the wire-bonded units and lids into the lid
attach equipment.
accurate lid attachment.
3. Lid attachment To attach the lid over the die cavity with a metal clip.
4. Unload (lid attach) To unload the carriers after lid attach.
5. Load (reflow) To load the lid-attached units into the reflow furnace.
6. Reflow To seal the lid on the substrate.
7. Unload (reflow) To unload the carriers after reflow.
* Underfill is more sensitive to moisture and can form voids which affect the part reliability.
Prebake and dispense are usually linked to avoid extended exposure for moisture
absorption again after prebake.
Marking Module
Marking Process Overview
• The MARKING process is broken down into 5 major steps:
1. Units Load 3. Marking
Objective:
To load the molded Objective:
strips or carriers To mark the
with the encapsulated units or
encapsulated units strips.
placed on them.
2. Pattern Recognition
System (PRS) 4. Units Unload
To recognize the To unload the marked
position of the units or strips.
encapsulated units
or strips with their
PRS eye points.

• The BALL ATTACH process is broken down into 9 major steps:
1. Units and 3. Pattern Recognition
Solder Sphere System (PRS) & Align
Load (BA) Objective:
with the units To align the balls to
placed on them. the theta (rotation)
To load the ball bin and X-Y position of
with solder spheres the units.
into the machine.
2. Screen Printing 4. Ball Placement
Objective:
Objective: To attach the balls onto
To print the flux the substrate
onto the substrate
bump solder.

5. Reflow 7. Load (Deflux)

To form the To load the carriers
interconnection into the deflux
between the die machine (if
and the substrate. needed).
6. Unload (Die
Attach) 8. Deflux
To unload the To remove flux
carriers after ball residue in between
attach. the balls. Units will
To unload the ball be dried after
bin when the defluxing.
remaining balls are
running out.
9. Unload (Deflux)
Objective:
To unload the carriers
from deflux machine.
Note: Solder paste can be used instead of flux for the ball attach
process.

Assembly Packaging Overview 2007 r2

Загружено:

Сведения о документе

Исходное описание:

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Assembly Packaging Overview 2007 r2

Загружено:

Авторское право:

Доступные форматы

Intel-USM

EBB526 Electronic Packaging

May 07 © Intel Malaysia 2007

May 07 © Intel Malaysia 2007 2

May 07 © Intel Malaysia 2007 3

May 07 © Intel Malaysia 2007 4

6. Second Level Interconnect

May 07 © Intel Malaysia 2007 5

8. Media and Packing

May 07 © Intel Malaysia 2007 6

May 07 © Intel Malaysia 2007

Land Grid Array Pin Grid Array Tape Carrier Transistor-

May 07 © Intel Malaysia 2007 8

Thermally enhanced Thermally enhanced flip Wafer-level Chip Size

May 07 © Intel Malaysia 2007 9

May 07 © Intel Malaysia 2007 10

1960 1970 1980 1990 2000 2010

May 07 © Intel Malaysia 2007 11

May 07 © Intel Malaysia 2007 14

– Ceramic is used as the conventional substrate material for high

May 07 © Intel Malaysia 2007 16

May 07 © Intel Malaysia 2007 17

 List five typical package types.

You are now ready to learn more details on

May 07 © Intel Malaysia 2007 18

 Wire bond interconnection packaging

Second level Wire

May 07 © Intel Malaysia 2007 19

– ProtectionEncapsulation Lid Mold compound

ENCAPSULATION SEALING MOLDING

– Second level interconnect

– Singulation Strip sawing

– Test & Inspection

May 07 © Intel Malaysia 2007 21

 Flip Chip interconnection packaging

Second level interconnection ball

Separated flip chip

– Second level interconnect

– Singulation Strip sawing

– Test & Inspection

May 07 © Intel Malaysia 2007 24

GLOB TOP ENCAPSULATION

Trim and form (if needed)

–Test & Inspection reel-to-reel

May 07 © Intel Malaysia 2007 26

May 07 © Intel Malaysia 2007 27

 List one of the typical packaging assembly

You are now ready to learn more details on

May 07 © Intel Malaysia 2007

May 07 © Intel Malaysia 2007 30

May 07 © Intel Malaysia 2007 31

2) Partial scribing (with

May 07 © Intel Malaysia 2007 33

May 07 © Intel Malaysia 2007 34

Deposited Process Method:

May 07 © Intel Malaysia 2007 35

Bump diameter 2R = (D2 + H2) / H

May 07 © Intel Malaysia 2007 36

May 07 © Intel Malaysia 2007 37

You are now ready to learn more details on

* Sometimes also called die bonding.

May 07 © Intel Malaysia 2007

May 07 © Intel Malaysia 2007 41