5/10/2011 Electronics and Communication Engineering Dept., MANIT
CADENCE VOLTAGESTOR D or Power and Power Rail Verification Complex power-sensitive designs increases the risk that IR drop will be a cause of silicon failure. Design teams require comprehensive power and power rail analysis solutions that can accurately validate on- chip power delivery networks, from initial power planning through final signoff prior to tape-out.
Within the Cadence Encounter digital IC design
platform, VoltageStorm power verification helps you quickly validate and optimize your power networks using both static and dynamic analysis approaches u
CADENCE VOLTAGESTOR D VoltageStorm power verification has been proven to validate IR drop and power electro migration (EM) D Up-front power rail analysis to help create robust power networks during power planning
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CADENCE VoltSto
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CADENCE VoltSto - lots
IR Drop
Current Density
Recommended De-coupling capacitance
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u C VoltSto - ts
D Enables efficient creation of on-chip power
networks D Minimizes risk of power-related silicon failures D Optimizes low-power designs D Delivers an efficient, hierarchical analysis solution D Supported by major reference flows, ASIC and IP vendors, and IDMs
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C VOLTAGESTOR- Ftu s
D POWER-DRIVEN DESIGN REQUIREMENTS
D POWERMETER POWER ESTIMATION D VOLTAGESTORM PE/DG D TRANSISTOR-LEVEL ANALYSIS D AUTOMATED DE-COUPLING CAPACITANCE OPTIMIZATION D IMPACT O IR DROP ON TIMING AND SI NOISE
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C VS- Sto SSTE REQUIREENTS Specific requirements are design dependent D 512MB (min) DRAM D 2GB (min) swap space D 50MB software disc space D 2GB per 1M gates design disc space LATFOROS D Sun Solaris 8 or 9 (32-bit, 64-bit) D HP-UX 11.0 (32-bit, 64-bit) D Opteron Linux RHEL 3.0 (64-bit) D Red Hat Linux RHEL 2.1 (32-bit) D BM AIX 5.1 (32-bit, 64-bit) INTERFACE D OpenAccess 2.2 u
