Logic Design(CS33)

Chapter 3: Logic Levels and families

Ms Veena V Desai
Assistant Professor
Department of Electronics and Communication Engineering
Gogte Institute of Technology
Udyambag, Belgaum-8. INDIA.
Email: karchiveena@yahoo.com
 Session 1
• Logic Levels
• Logic Families
• Integration Levels
• Switching Times
• Propagation Delay
• Fan-in and Fan-out
 Binary Logic Values

• Logic ‘1’
• Logic ‘0’
• Undefined value
 Logic Levels

• Positive Binary Logic System

High level - logic 1
Low level - logic 0
• Negative Binary Logic System
High level - logic 0
Low level - logic 1
 Positive and Negative Logic

Positive Negative
Logic Logic
Logic H Logic H
value 1 value 0
Logic L Logic L
value 0 value 1
 TTL Logic Levels
• Logic ‘1’ - VH
2.4V VH  5V

• Logic ‘0’ - VL
0V VL  0.4 V

• Undefined
0.4 V < V < 2.4 V
 TTL Logic Levels

• Floating signals may take on illegal values

• What happens during a signal transition?

Logic ‘1’
2.4V
Undefined
0.4V
Logic ‘0’
 Classification of Logic Families

Logic families are classified based on

• Devices Used
example: diodes ,transistors etc.
• Structure of Digital Circuits
example: MOSFET(PMOS,NMOS)
 Examples of Logic Families

• DTL :Diode Transistor Logic

• RTL :Resistor Transistor Logic
• TTL :Transistor Transistor Logic
• ECL :Emitter Coupled Logic
• CMOS :Complementary MOSFET Logic
 Logic Families Differ In:

• Logic Levels
• Propagation Delays
• Driving Capabilities
• Other Parameters
 Electrical Characteristics
of Logic Families(Noise margins)

• VOHmin min value of output recognised as a ‘1’ logic 1

• VIHmin min value input recognised as a ‘1’

indeterminate
• VILmax max value of input recognised as a ‘0’ voltage
• VOLmax max value of output recognised as a ‘0’

• Values outside the given range are not allowed. logic 0

 TTL and CMOS
(basic structures)
MOSFET
BJT Transistor Types (NMOS, PMOS)

TTL Logic Gate Families CMOS

 TTL and CMOS
(Characteristics)
TTL CMOS
•Faster •Low power
•Stronger drive consumption
capability •Simpler to make
•Greater packing
density
•Better noise immunity
 Integration levels
• SSI -small scale integration
• MSI -medium scale integration
• LSI -large scale integration
• VLSI -very large scale integration
• ULSI -ultra large scale integration
• GSI -giant scale integration
Complexity of a single chip is called Scale
of Integration.
 Integration Levels
(comparison)
Levels of Transistors Gates/ Applications
integration /package chip
SSI 1-100 <12 Logic gates
Op-amps
MSI 100-1000 12-99 Registers
Filters
LSI 1000-10000 1000 8 bit processor,
A/D converter
 ….contd
VLSI 10k gates/chip 16,32 bit processor
256KB memory
DS processor
ULSI 100k gates/chip 64 bit processor
8 MB memory
Image processor
GSI 1M gates/chip 64 MB memory
multiprocessor
 Switching Time
Vo

tr tf
Vdd
90% Vdd

10% Vdd

tLH tHL
 Output Switching Times

• tLH- low to high rise time (tr)

Time interval between 10% to 90% of Vdd

• tHL- high to low time or fall time (tf)

Time for signal to fall from 90%Vdd to
10%Vdd
 Maximum Switching Frequency
• Switching is fast with
tmin=thl+tlh

• Max switching freq is given by fmax=1/tmin

• Eg: thl =0.5 nsec, tlh=1.0 nsec

tmin =1.5 nsec
fmax=1/ tmin=666.67Mhz
 Propagation Delay

It is the physical delay as the logical signal

propagates through the gates.
 tplh and tphl
• tplh-is the propagation delay component for
an output high to low transition.
– It is the time which elapses from the instance
the input reaches 50% of VDD to the time the
output reaches 50% of VDD.
• tphl –is the propagation delay component for
an output low to high transition.
 Fan-out

Fan-out of a gate is the number of gates

driven by that gate i.e the maximum
number of gates (load ) that can exist
without impairing the normal operation of
the gate.
 Fan-out Of Inverter
No Load :Fan-out is 0

Load: Fan-out is 1

With 3 inverter load:Fan-out is 3

 Fan-in
Fan-in of a gate is the number of inputs that
can be connected to it without impairing the
normal operation of the gate.
 Fan-in Of a gate
Number of inputs to a logic gate
example: for NAND gate with n inputs
n = 2: Fan-in:2
n = 3: Fan-in:3
n = 4: Fan-in:4
Other details to be considered…

• Extension of propagation delay concepts to

other logic gates. eg:AND gate, OR gate.
• Effect of Fan-in and Fan-out on logic
cascades.
 Summary

• Interpreted Logic Levels

• Differentiated and Compared Logic
Families
• Defined Switching Times,Propagation
Delay , Fan-in and Fan-out
• Examples